Datasheet ADN2805 (Analog Devices) - 10

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ADN2805 Data Sheet THEORY OF OPERATION
The ADN2805 is a delay- and phase-locked loop circuit for
psh
clock recovery and data retiming from an NRZ encoded data
X(s) e(s)
stream. The phase of the input data signal is tracked by two
INPUT DATA d/sc o/s
separate feedback loops that share a common control voltage. A high speed delay-locked loop path uses a voltage controlled
Z(s) 1/n RECOVERED
phase shifter to track the high frequency components of input
CLOCK
jitter. A separate phase control loop, comprised of the VCO,
d = PHASE DETECTOR GAIN JITTER TRANSFER FUNCTION
tracks the low frequency components of input jitter. The initial
o = VCO GAIN c = LOOP INTEGRATOR Z(s) 1 =
frequency of the VCO is set by yet a third loop, which compares
psh = PHASE SHIFTER GAIN X(s) cn n psh n = DIVIDE RATIO s2 + s + 1 do o
the VCO frequency with the input data frequency and sets the
TRACKING ERROR TRANSFER FUNCTION
coarse tuning voltage. The jitter tracking phase-locked loop
e(s) s2 =
11 (PLL) controls the VCO by the fine-tuning control.
X(s) do
0
s2 d psh + s +
1-
c cn
712 0 The delay and phase loops together track the phase of the input Figure 11. ADN2805 PLL/DLL Architecture data signal. For example, when the clock lags input data, the phase detector drives the VCO to a higher frequency and
JITTER PEAKING IN ORDINARY PLL
increases the delay through the phase shifter; both of these actions serve to reduce the phase error between the clock and data. The faster clock picks up phase, while simultaneously, the delayed data loses phase. Because the loop filter is an integrator,
) B
the static phase error is driven to zero.
d ( IN
Another view of the circuit is that the phase shifter implements
GA R
the zero required for frequency compensation of a second-order
E ADN2805 T Z(s)
phase-locked loop, and this zero is placed in the feedback path
JIT X(s)
and, thus, does not appear in the closed-loop transfer function. Jitter peaking in a conventional second-order phase-locked loop is caused by the presence of this zero in the closed-loop transfer
o d psh n psh c
12 0 function. Because this circuit has no zero in the closed-loop 1-
FREQUENCY (kHz)
12 07 transfer, jitter peaking is minimized. Figure 12. ADN2805 Jitter Response vs. Conventional PLL The delay and phase loops together simultaneously provide The delay and phase loops contribute to overall jitter accom- wideband jitter accommodation and narrow-band jitter modation. At low frequencies of input jitter on the data signal, filtering. The linearized block diagram in Figure 11 shows that the integrator in the loop filter provides high gain to track large the jitter transfer function, Z(s)/X(s), is second-order low-pass, jitter amplitudes with small phase error. In this case, the VCO is providing excellent filtering. Note that the jitter transfer has no frequency modulated and jitter is tracked as in an ordinary zero, unlike an ordinary second-order phase-locked loop. This phase-locked loop. The amount of low frequency jitter that can means that the main PLL has virtually zero jitter peaking (see be tracked is a function of the VCO tuning range. A wider Figure 12). This makes this circuit ideal for signal regenerator tuning range gives larger accommodation of low frequency applications where jitter peaking in a cascade of regenerators jitter. The internal loop control voltage remains small for small can contribute to hazardous jitter accumulation. phase errors; therefore, the phase shifter remains close to the The error transfer, e(s)/X(s), has the same high-pass form as an center of its range and thus contributes little to the low ordinary phase-locked loop. This transfer function is free to be frequency jitter accommodation. optimized to give excellent wideband jitter accommodation At medium jitter frequencies, the gain and tuning range of the because the jitter transfer function, Z(s)/X(s), provides the VCO are not large enough to track input jitter. In this case, the narrow-band jitter filtering. VCO control voltage becomes large and saturates, and the VCO frequency dwells at either one extreme of its tuning range or at the other. The size of the VCO tuning range, therefore, has only a small effect on the jitter accommodation. As such, the delay- locked loop control voltage is larger, and, consequently, the phase shifter takes on the burden of tracking the input jitter. The phase shifter range, in UI, can be seen as a broad plateau on the jitter tolerance curve. The phase shifter has a minimum range of 2 UI at all data rates. Rev. B | Page 10 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS JITTER SPECIFICATIONS OUTPUT AND TIMING SPECIFICATIONS Timing Characteristics ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Thermal Resistance ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION THEORY OF OPERATION FUNCTIONAL DESCRIPTION FREQUENCY ACQUISITION INPUT BUFFER LOCK DETECTOR OPERATION Normal Mode LOL Detector Operation Using a Reference Clock Static LOL Mode SQUELCH MODE SYSTEM RESET I2C INTERFACE APPLICATIONS INFORMATION PCB DESIGN GUIDELINES Power Supply Connections and Ground Planes Transmission Lines Soldering Guidelines for Lead Frame Chip Scale Package OUTLINE DIMENSIONS ORDERING GUIDE