Datasheet ADSP-21371, ADSP-21375 (Analog Devices) - 9

ADSP-21371 /ADSP-21375
Serial ports operate in five modes: but data is sent to the FIFO as 32-bit words (that is, one-half of a • Standard DSP serial mode frame at a time). The processor supports 24- and 32-bit I2S, 24- and 32-bit left-justified, and 24-, 20-, 18- and 16-bit right-justi- • Multichanne l (TDM) mode with support for packed I2S fied formats. mode
Precision Clock Generator (PCG)
• I2S mode The precision clock generators (PCG) consist of four units, each • Packed I2S mode of which generates a pair of signals (clock and frame sync) • Left-justified sample pair mode derived from a clock input signal. The units, A B, C, and D, are Left-justified sample pair mode is a mode where in each frame identical in functionality and operate independently of each sync cycle two samples of data are transmitted/received—one other. The two signals generated by each unit are normally used sample on the high segment of the frame sync, the other on the as a serial bit clock/frame sync pair. low segment of the frame sync. Programs have control over var-
Digital Peripheral Interface (DPI)
ious attributes of this mode. The digital peripheral interface provides connections to two Each of the serial ports supports the left-justified sample pair serial peripheral interface (SPI) ports, one universal asynchro- and I2S protocols (I2S is an industry-standard interface com- nous receiver-transmitter (UART), 12 flags, a 2-wire interface monly used by audio codecs, ADCs, and DACs such as the (TWI), and two general-purpose timers. Analog Devices AD183x family), with two data pins, allowing four left-justified sample pair or I2S channels (using two stereo
Serial Peripheral (Compatible) Interface
devices) per serial port, with a maximum of up to 32 I2S chan- The ADSP-21371/ADSP-21375 SHARC processors contain two nels. The serial ports permit little-endian or big-endian serial peripheral interface ports (SPIs). The SPI is an industry- transmission formats and word lengths selectable from 3 bits to standard synchronous serial link, enabling the SPI-compatible 32 bits. For the left-justified sample pair and I2S modes, data- ports of the processors to communicate with other SPI compati- word lengths are selectable between 8 bits and 32 bits. Serial ble devices. The SPI consists of two data pins, one device select ports offer selectable synchronization and transmit modes as pin, and one clock pin. It is a full-duplex synchronous serial well as optional -law or A-law companding selection on a per interface, supporting both master and slave modes. The SPI port channel basis. Serial port clocks and frame syncs can be inter- can operate in a multimaster environment by interfacing with nally or externally generated. up to four other SPI-compatible devices, either acting as a mas- The serial ports also contain frame sync error detection logic ter or slave device. where the serial ports detect frame syncs that arrive early (for The SPI-compatible peripheral implementation also features example frame syncs that arrive while the transmission/recep- programmable baud rates and clock phases and polarities. The tion of the previous word is occurring). All the serial ports also SPI-compatible port uses open drain drivers to support a multi- share one dedicated error interrupt. master configuration and to avoid data contention.
S/PDIF-Compatible Digital Audio Receiver/Transmitter UART Port
The ADSP-21371 S/PDIF receiver/transmitter has no separate The processors provide a full-duplex Universal Asynchronous DMA channels. It receives audio data in serial format and con- Receiver/Transmitter (UART) port, which is fully compatible verts it into a biphase encoded signal. The serial data input to with PC-standard UARTs. The UART port provides a simpli- the receiver/transmitter can be formatted as left justified, I2S or fied UART interface to other peripherals or hosts, supporting right justified with word widths of 16, 18, 20, or full-duplex, DMA-supported, asynchronous transfers of serial 24 bits. data. The UART also has multiprocessor communication capa- The serial data, clock, and frame sync inputs to the S/PDIF bility using 9-bit address detection. This allows it to be used in receiver/transmitter are routed through the signal routing unit multidrop networks through the RS-485 data interface stan- (SRU). They can come from a variety of sources such as the dard. The UART port also includes support for 5 to 8 data bits, 1 SPORTs, external pins, the precision clock generators (PCGs), or 2 stop bits, and none, even, or odd parity. The UART port and are controlled by the SRU control registers. supports two modes of operation: The ADSP-21375 does not have an S/PDIF-compatible digital • PIO (programmed I/O) – The processor sends or receives receiver/transmitter. data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive.
Input Data Port (IDP)
• DMA (direct memory access) – The DMA controller trans- The IDP provides up to eight serial input channels—each with fers both transmit and receive data. This reduces the its own clock, frame sync, and data inputs. The eight channels number and frequency of interrupts required to transfer are automatically multiplexed into a single 32-bit by eight-deep data to and from memory. The UART has two dedicated FIFO. Data is always formatted as a 64-bit frame and divided into two 32-bit words. The serial protocol is designed to receive audio channels in I2S, left-justified sample pair, or right-justified mode. One frame sync cycle indicates one 64-bit left/right pair, Rev. D | Page 9 of 56 | April 2013 Document Outline Summary Dedicated Audio Components Table Of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of an Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture External Port SDRAM Controller External Memory Code Execution External Port Throughput Asynchronous Memory Controller Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Input Data Port (IDP) Precision Clock Generator (PCG) Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface UART Port Peripheral Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions ADSP-21371/ADSP-21375 Specifications Operating Conditions Electrical Characteristics Package Information Maximum Power Dissipation Absolute Maximum Ratings ESD Sensitivity Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Core Timer Interrupts Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing Memory Read—Bus Master Memory Write—Bus Master Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (HFCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing TWI Controller Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 208-Lead LQFP_EP Pinout Package Dimensions Automotive Products Ordering Guide