Datasheet ADSP-21371, ADSP-21375 (Analog Devices) - 10

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ADSP-21371/ ADSP-21375
DMA channels, one for transmit and one for receive. These port (PDAP), or the UART (see Table 7). DMA channels have lower default priority than most DMA channels because of their relatively low service rates.
Table 7. DMA Channels
The UART port’s baud rate, serial data format, error code gen-
Peripheral ADSP-21371 ADSP-21375
eration and status, and interrupts are programmable. The port: SPORT 16 8 • Supports bit rates ranging from (fPCLK/1,048,576) to PDAP 8 8 (fPCLK/16) bits per second. SPI 2 2 • Supports data formats from 7 to 12 bits per frame. UART 2 2 • Can be configured to generate maskable interrupts for both EP 2 2 transmit and receive operations. MTM/DTCP 2 2 In conjunction with the general-purpose timer functions, auto- Total DMA Channels 32 24 baud detection is supported.
Peripheral Timers Delay Line DMA
Two general-purpose timers can generate periodic interrupts The processors provide delay line DMA functionality. This and be independently set to operate in one of three modes: allows processor reads and writes to external delay line buffers (and hence to external memory) with limited core interaction. • Pulse waveform generation mode • Pulse width count/capture mode
Scatter/Gather DMA
• External event watchdog mode The ADSP-2137x processor provides scatter/gather DMA func- tionality. This allows processor DMA reads/writes to/from non- Each general-purpose timer has one bidirectional pin and four contiguous memory blocks. registers that implement its mode of operation: a 6-bit configu- ration register, a 32-bit count register, a 32-bit period register,
SYSTEM DESIGN
and a 32-bit pulse width register. A single control and status The following sections provide an introduction to system design register enables or disables the general-purpose timers options and power supply issues. For complete system design independently. information, see the ADSP-2137x SHARC Processor Hardware
2-Wire Interface Port (TWI)
Reference. The TWI is a bidirectional 2-wire serial bus used to move 8-bit
Program Booting
data while maintaining compliance with the I2C bus protocol. The TWI master incorporates the following features: The internal memory of the processor boots at system power-up from an 8-bit EPROM via the external port, an SPI master, or an • Simultaneous master and slave operation on multiple SPI slave. Booting is determined by the boot configuration device systems with support for multi master data (BOOT_CFG1–0) pins in Table 8. Selection of the boot source arbitration is controlled via the SPI as either a master or slave device, or it • Digital filtering and timed event processing can immediately begin executing from ROM. • 7-bit addressing
Table 8. Boot Mode Selection
• 100 kbps and 400 kbps data rates
BOOT_CFG1–0 Booting Mode
• Low interrupt rate 00 SPI Slave Boot
I/O PROCESSOR FEATURES
01 SPI Master Boot The I/O processor provides many channels of DMA and con- 10 EPROM/FLASH Boot trols the extensive set of peripherals described in the previous 11 No boot (processor executes from sections. internal ROM after reset)
DMA Controller
The “Running Reset” feature allows programs to perform a reset The processor’s on-chip DMA controller allows data transfers of the processor core and peripherals, but without resetting the without processor intervention. The DMA controller operates PLL and SDRAM controller, or performing a boot. The RESET- independently and invisibly to the processor core, allowing OUT pin acts as the input for initiating a running reset. DMA operations to occur while the core is simultaneously exe- cuting its program instructions. DMA transfers can occur between the ADSP-2137x processor’s internal memory and its serial ports, the SPI-compatible (serial peripheral interface) ports, the IDP (input data port), the parallel data acquisition Rev. D | Page 10 of 56 | April 2013 Document Outline Summary Dedicated Audio Components Table Of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of an Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture External Port SDRAM Controller External Memory Code Execution External Port Throughput Asynchronous Memory Controller Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Input Data Port (IDP) Precision Clock Generator (PCG) Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface UART Port Peripheral Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions ADSP-21371/ADSP-21375 Specifications Operating Conditions Electrical Characteristics Package Information Maximum Power Dissipation Absolute Maximum Ratings ESD Sensitivity Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Core Timer Interrupts Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing Memory Read—Bus Master Memory Write—Bus Master Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (HFCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing TWI Controller Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 208-Lead LQFP_EP Pinout Package Dimensions Automotive Products Ordering Guide