Datasheet ADSP-21477, ADSP-21478, ADSP-21479 (Analog Devices) - 10

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ADSP-21477 /ADSP-21478 /ADSP-21479
occupy a 8M word window in the processor’s address space but, Serial ports operate in five modes: if not fully populated, these windows are not made contiguous • Standard serial mode by the memory controller logic. • Multichanne l (TDM) mode
External Port Throughput
• I2S mode The throughput for the external port, based on 133 MHz clock • Packed I2S mode and 16-bit data bus, is 88 Mbytes/sec for the AMI and 266 Mbytes/sec for SDRAM. • Left-justified mode
MediaLB S/PDIF-Compatible Digital Audio Receiver/Transmitter
The automotive models of the processors have an MLB interface The S/PDIF receiver/transmitter has no separate DMA chan- which allows the processor to function as a media local bus nels. It receives audio data in serial format and converts it into a device. It includes support for both 3-pin and 5-pin MLB proto- bi phase encoded signal. The serial data input to the cols. It supports speeds up to 1024 FS (49.25M bits/sec, receiver/transmitter can be formatted as left justified, I2S or FS = 48.1 kHz) and up to 31 logical channels, with up to right-justified with word widths of 16, 18, 20, or 24 bits. 124 bytes of data per media local bus frame. For a list of auto- The serial data, clock, and frame sync inputs to the S/PDIF motive products, see Automotive Products. receiver/transmitter are routed through the signal routing unit (SRU). They can come from a variety of sources, such as the
Digital Applications Interface (DAI)
SPORTs, external pins, the precision clock generators (PCGs), The digital applications interface (DAI) provides the ability to and are controlled by the SRU control registers. connect various peripherals to any of the DAI pins
Asynchronous Sample Rate Converter (SRC)
(DAI_P20–1). The sample rate converter contains four blocks and is the same Programs make these connections using the signal routing unit core as that used in the AD1896 192 kHz stereo asynchronous (SRU), shown in Figure 1. sample rate converter. The SRC block provides up to 128 dB The SRU is a matrix routing unit (or group of multiplexers) that SNR and is used to perform synchronous or asynchronous sam- enables the peripherals provided by the DAI to be intercon- ple rate conversion across independent stereo channels, without nected under software control. This allows easy use of the DAI using internal processor resources. The four SRC blocks can associated peripherals for a much wider variety of applications also be configured to operate together to convert multichannel by using a larger set of algorithms than is possible with non con- audio data without phase mismatches. Finally, the SRC can be figurable signal paths. used to clean up audio data from jittery clock sources such as The associated peripherals include eight serial ports, four preci- the S/PDIF receiver. sion clock generators (PCG), a S/PDIF transceiver, four ASRCs,
Input Data Port
and an input data port (IDP). The IDP provides an additional input path to the SHARC core, configurable as either eight The IDP provides up to eight serial input channels—each with channels of serial data, or a single 20-bit wide synchronous par- its own clock, frame sync, and data inputs. The eight channels allel data acquisition port. Each data channel has its own DMA are automatically multiplexed into a single 32-bit by eight-deep channel that is independent from the processor’s serial ports. FIFO. Data is always formatted as a 64-bit frame and divided into two 32-bit words. The serial protocol is designed to receive
Serial Ports (SPORTs)
audio channels in I2S, left-justified sample pair, or right-justified The processors feature eight synchronous serial ports that pro- mode. vide an inexpensive interface to a wide variety of digital and The IDP also provides a parallel data acquisition port (PDAP) mixed-signal peripheral devices such as Analog Devices’ which can be used for receiving parallel data. The PDAP port AD183x family of audio codecs, ADCs, and DACs. The serial has a clock input and a hold input. The data for the PDAP can ports are made up of two data lines, a clock, and frame sync. The be received from DAI pins or from the external port pins. The data lines can be programmed to either transmit or receive and PDAP supports a maximum of 20-bit data and four different each data line has a dedicated DMA channel. packing modes to receive the incoming data. Serial ports can support up to 16 transmit or 16 receive DMA
Precision Clock Generators
channels of audio data when all eight SPORTs are enabled, or four full duplex TDM streams of 128 channels per frame. The precision clock generators (PCG) consist of four units, each of which generates a pair of signals (clock and frame sync) Serial port data can be automatically transferred to and from derived from a clock input signal. The units, A B, C, and D are on-chip memory/external memory via dedicated DMA chan- identical in functionality and operate independently of each nels. Each of the serial ports can work in conjunction with other. The two signals generated by each unit are normally used another serial port to provide TDM support. One SPORT pro- as a serial bit clock/frame sync pair. vides two transmit signals while the other SPORT provides the two receive signals. The frame sync and clock are shared. The outputs of PCG A and B can be routed through the DAI pins and the outputs of PCG C and D can be driven on to the DAI as well as the DPI pins. Rev. D | Page 10 of 76 | April 2017 Document Outline SHARC Processor Summary Revision History Product Application Restriction General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory On-Chip Memory Bandwidth ROM Based Security Digital Transmission Content Protection Family Peripheral Architecture External Memory External Port SIMD Access to External Memory VISA and ISA Access to External Memory SDRAM Controller Asynchronous Memory Controller External Port Throughput MediaLB Digital Applications Interface (DAI) Serial Ports (SPORTs) S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter (SRC) Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface (SPI) UART Port Pulse-Width Modulation Timers 2-Wire Interface Port (TWI) Shift Register I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA FFT Accelerator FIR Accelerator IIR Accelerator Watchdog Timer (WDT) Real-Time Clock System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Maximum Power Dissipation Package Information ESD Sensitivity Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Watchdog Timer Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing AMI Read AMI Write Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Shift Register Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics Thermal Diode 88-LFCSP_VQ Lead Assignment 100-LQFP_EP Lead Assignment 196-BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide