Datasheet ADSP-21477, ADSP-21478, ADSP-21479 (Analog Devices)

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SHARC Processor ADSP-21477/ ADSP-21478/ ADSP-21479 SUMMARY The ADSP-2147x processors are available with unique audio-centric peripherals, such as the digital applications High performance 32-bit/40-bit floating-point processor interface, serial ports, precision clock generators, S/PDIF optimized for high performance audio processing transceiver, asynchronous sample rate converters, input Single-instruction, multiple-data (SIMD) computational data port, and more. architecture Factory programmed ROM versions containing latest audio On-chip memory—up to 5M bits of on-chip RAM, 4M bits of decoders from Dolby and DTS, available to IP licenses on-chip ROM For complete ordering information, see Ordering Guide . Up to 300 MHz operating frequency Qualified for automotive applications. See Automotive Products Code compatible with all other members of the SHARC family Internal Memory SIMD Core Block 0 Block 1 Block 2 Block 3 RAM/ROM RAM/ROM RAM RAM Instruction 5 Stage Cache Sequencer B0D B1D B2D B3D Core 64-BIT 64-BIT 64-BIT 64-BIT
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DAG1/2 Timer DMD DMD 64-BIT 64-BIT PEx PEy Core Bus Internal Memory I/F Cross Bar PMD PMD 64-BIT 64-BIT FLAGx/IRQx/ THERMAL IOD0 32-BIT EPD BUS 64-BIT JTAG TMREXP DIODE IOD1 PERIPHERAL BUS 32-BIT 32-BIT IOD0 BUS FFT DTCP/ FIR MTM IIR PERIPHERAL BUS EP SPEP BUS CORE PCG TIMER SHIFT S/PDIF PCG ASRC PDAP/ SPORT CORE PWM FLAGS/ TWI SPI/B UART AMI SDRAM RTC WDT MLB C-D 1-0 REG Tx/Rx A-D 3-0 IDP 7-0 FLAGS 3-0 CTL PWM3-1 7-0 DPI Routing/Pins DAI Routing/Pins External Port Pin MUX External DPI Peripherals DAI Peripherals Peripherals Port
Figure 1. Functional Block Diagram SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
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Document Outline SHARC Processor Summary Revision History Product Application Restriction General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory On-Chip Memory Bandwidth ROM Based Security Digital Transmission Content Protection Family Peripheral Architecture External Memory External Port SIMD Access to External Memory VISA and ISA Access to External Memory SDRAM Controller Asynchronous Memory Controller External Port Throughput MediaLB Digital Applications Interface (DAI) Serial Ports (SPORTs) S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter (SRC) Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface (SPI) UART Port Pulse-Width Modulation Timers 2-Wire Interface Port (TWI) Shift Register I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA FFT Accelerator FIR Accelerator IIR Accelerator Watchdog Timer (WDT) Real-Time Clock System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Maximum Power Dissipation Package Information ESD Sensitivity Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Watchdog Timer Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing AMI Read AMI Write Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Shift Register Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics Thermal Diode 88-LFCSP_VQ Lead Assignment 100-LQFP_EP Lead Assignment 196-BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide