Datasheet HMC988LP3E (Analog Devices) - 3

HMC988LP3E
v04.1014
PROGRAMMABLE CLOCK DIVIDER AND DELAY DC - 4 GHz Table 1. Electrical Specifications
t unless otherwise specified: t = +25 °C. Current consumptions assumes fine adjustable delay is disabled. Phase M noise degrades approximately 15 db if using fine delay adjustment. s Parameter Conditions Min typ. Max units AM -40 -50 dbc n - bypass regulator PM -50 -70 dbc io Current Consumption t using regulator case 0.7 mA stand-by Current - Chip Disabled u bypass regulator case 0.01 mA ib Mininum Current [9] 68 mA r Additive Divider 16 21 mA t Delay line Current 12 44 mA is lVPECl termination load Current 26 40 mA Propagation Delay Delay line Disabled 210 ps 250 MHz (setpoint 15) 350 fs/ °C k D Delay vs temp 1 GHz (setpoint 15) 150 fs/ °C C
Logic Inputs: CHIP0, CHIP1, CHIP 2, SLE,SDI, SCK, TRIG
input logic low, Vil 0.9 V lo input logic High, Vih 2.1 V C [1] using standard lVPECl termination as shown in Figure 9 [2] When reg04[03]=1, Default setting=0 [3] Phase noise performance is characterized using the HMC1034 as a source at ~2 GHz, 9 dbm differential. For sinusoidal low-frequency inputs, the phase noise may degrade. For example, a single-ended 100 MHz 9 dbm sin-wave in bypass mode produces a phase noise floor of -164 dbc/ Hz as opposed to -170 dbc/Hz. [4] to calculate Jitter Density, (√2*10^((Floor phase noise)/20)/2π)*(1/frequency) i.e jitter density@ 500 MHz = (√2*10^(-168/20)/2π)*(1/500000000) [5] integrated bandwidth start from 12 kHz to 20 MHz, Jitter Density x √Desired customized bW i.e integrated jitter @ 2 GHz over a 6 GHz bW = 0.7 asec/√Hz x √6 GHz 1asec = 1/1000 of a femtosecond. only 100 MHz number is meaured with 100 MHz Wenzel and HMC988 in bypass mode [6] these integrated jitter number are based on calculation. [7] the fine delay adjustment is valid up to a 1 GHz output frequency. Maximum frequency is 650MHz with divider bypassed (divide-by-1). [8] spur caused by 100 mVpp Agressor tone on input supply. this specification is the level of the ssb spur which appears symmetrically around the output frequency when the input supply stimulated by a 100 mVpp aggressive tone @ 30 kHz. the spur level is linearly proportional to the aggres- sor tone amplitude. it is relatively independent of input and output frequencies, and input power level. When regulated, at least 3.7 V must be applied to the input power supply to provide sufficient Psrr. the spur level is not appreciably different for single ended or differential operation. the frequency response to the aggressive tone is flat from 1 kHz to 50 kHz offset. Above 50 kHz the solution Psrr improves strongly, but is largely dependant on board decoupling capacitance and is not a direct indication of the raw part performance. [9] When Divider is bypassed,no termination loads and delay line disabled case. Inf F or o m r p atio r n ifc ur e n , d ishe e d lbiv y e A r n y a alog n D d t evic o p es is la beclie o eved rd to ebre sa: H ccur iattti e tae M nd re ilicarbloew . H a o ve C wever, o n rp o For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other oration, 2 Elizabeth Drive, Chelmsford, MA 01824 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 978-250-3343 Fax: 978-250-3373 O rights of third parties that may result from its use. Specifications subject to change without notice. No P rd hone e r O : 7 n 81- -3li 2n 9 e a -47 t w 0 w 0 • O w rd .h e it r o t niltie n .c e ao t m
3
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. www.analog.com Application Support: Pho Trademarks and registered trademarks are the property of their respective owners. ne: 978-250-33 A 4 p 3 o plica r a tio p n S p u s p @ po h rt itt : P ite ho . n c e o : 1m -800-ANALOG-D