Datasheet ADSP-BF531, ADSP-BF532, ADSP-BF533 (Analog Devices) - 7

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ADSP-BF531/ ADSP-BF532 /ADSP-BF533
Each event type has an associated register to hold the return
Table 3. System Interrupt Controller (SIC)
address and an associated return-from-event instruction. When an event is triggered, the state of the processor is saved on the
Peripheral Interrupt Event Default Mapping
supervisor stack. PLL Wakeup IVG7 The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors’ event DMA Error IVG7 controller consists of two stages, the core event controller (CEC) PPI Error IVG7 and the system interrupt controller (SIC). The core event con- SPORT 0 Error IVG7 troller works with the system interrupt controller to prioritize SPORT 1 Error IVG7 and control all system events. Conceptually, interrupts from the peripherals enter into the SIC, and are then routed directly into SPI Error IVG7 the general-purpose interrupts of the CEC. UART Error IVG7 Real-Time Clock IVG8
Core Event Controller (CEC)
DMA Channel 0 (PPI) IVG8 The CEC supports nine general-purpose interrupts (IVG15–7), DMA Channel 1 (SPORT 0 Receive) IVG9 in addition to the dedicated interrupt and exception events. Of DMA Channel 2 (SPORT 0 Transmit) IVG9 these general-purpose interrupts, the two lowest priority inter- rupts (IVG15–14) are recommended to be reserved for software DMA Channel 3 (SPORT 1 Receive) IVG9 interrupt handlers, leaving seven prioritized interrupt inputs to DMA Channel 4 (SPORT 1 Transmit) IVG9 support the peripherals of the processor. Table 2 describes the DMA Channel 5 (SPI) IVG10 inputs to the CEC, identifies their names in the event vector DMA Channel 6 (UART Receive) IVG10 table (EVT), and lists their priorities. DMA Channel 7 (UART Transmit) IVG10
Table 2. Core Event Controller (CEC)
Timer 0 IVG11 Timer 1 IVG11
Priority
Timer 2 IVG11
(0 is Highest) Event Class EVT Entry
Port F GPIO Interrupt A IVG12 0 Emulation/Test Control EMU Port F GPIO Interrupt B IVG12 1 Reset RST Memory DMA Stream 0 IVG13 2 Nonmaskable Interrupt NMI Memory DMA Stream 1 IVG13 3 Exception EVX Software Watchdog Timer IVG13 4 Reserved 5 Hardware Error IVHW
Event Control
6 Core Timer IVTMR The processors provide a very flexible mechanism to control the 7 General Interrupt 7 IVG7 processing of events. In the CEC, three registers are used to 8 General Interrupt 8 IVG8 coordinate and control events. Each register is 32 bits wide: 9 General Interrupt 9 IVG9 • CEC interrupt latch register (ILAT) – The ILAT register 10 General Interrupt 10 IVG10 indicates when events have been latched. The appropriate bit is set when the processor has latched the event and 11 General Interrupt 11 IVG11 cleared when the event has been accepted into the system. 12 General Interrupt 12 IVG12 This register is updated automatically by the controller, but 13 General Interrupt 13 IVG13 it can also be written to clear (cancel) latched events. This 14 General Interrupt 14 IVG14 register can be read while in supervisor mode and can only 15 General Interrupt 15 IVG15 be written while in supervisor mode when the correspond- ing IMASK bit is cleared.
System Interrupt Controller (SIC)
• CEC interrupt mask register (IMASK) – The IMASK regis- The system interrupt controller provides the mapping and rout- ter controls the masking and unmasking of individual ing of events from the many peripheral interrupt sources to the events. When a bit is set in the IMASK register, that event is prioritized general-purpose interrupt inputs of the CEC. unmasked and is processed by the CEC when asserted. A Although the processors provide a default mapping, the user cleared bit in the IMASK register masks the event, can alter the mappings and priorities of interrupt events by writ- preventing the processor from servicing the event even ing the appropriate values into the interrupt assignment though the event may be latched in the ILAT register. This registers (SIC_IARx). Table 3 describes the inputs into the SIC register can be read or written while in supervisor mode. and the default mappings into the CEC. Note that general-purpose interrupts can be globally enabled and disabled with the STI and CLI instructions, respectively. Rev. I | Page 7 of 64 | August 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Port General-Purpose I/O Port F Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing General-Purpose I/O Port F Pin Cycle Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 160-Ball CSP_BGA Ball Assignment 169-Ball PBGA Ball Assignment 176-Lead LQFP Pinout Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide