Datasheet ADSP-BF531, ADSP-BF532, ADSP-BF533 (Analog Devices) - 6

ADSP-BF531/ ADSP-BF532 /ADSP-BF533 0xFFFF FFFF 0xFFFF FFFF CORE MMR REGISTERS (2M BYTE) CORE MMR REGISTERS (2M BYTE) 0xFFE0 0000 0xFFE0 0000 SYSTEM MMR REGISTERS (2M BYTE) SYSTEM MMR REGISTERS (2M BYTE) 0xFFC0 0000 0xFFC0 0000 RESERVED RESERVED 0xFFB0 1000 0xFFB0 1000 SCRATCHPAD SRAM (4K BYTE) SCRATCHPAD SRAM (4K BYTE) 0xFFB0 0000 0xFFB0 0000 RESERVED RESERVED AP 0xFFA1 4000 P 0xFFA1 4000 M INSTRUCTION SRAM/CACHE (16K BYTE) A INSTRUCTION SRAM/CACHE (16K BYTE) Y M R 0xFFA1 0000 Y 0xFFA1 0000 O RESERVED R INSTRUCTION SRAM (64K BYTE) O EM 0xFFA0 C000 M 0xFFA0 0000 M INSTRUCTION SRAM (16K BYTE) E RESERVED L M 0xFFA0 8000 A 0xFF90 8000 L N RESERVED A DATA BANK B SRAM/CACHE (16K BYTE) 0xFFA0 0000 N ER 0xFF90 4000 R T RESERVED E DATA BANK B SRAM (16K BYTE) IN T 0xFF90 8000 0xFF90 0000 IN RESERVED RESERVED 0xFF90 4000 0xFF80 8000 RESERVED DATA BANK A SRAM/CACHE (16K BYTE) 0xFF80 8000 0xFF80 4000 DATA BANK A SRAM/CACHE (16K BYTE) DATA BANK A SRAM (16K BYTE) 0xFF80 4000 0xFF80 0000 RESERVED RESERVED 0xEF00 0000 0xEF00 0000 RESERVED P RESERVED 0x2040 0000 P A 0x2040 0000 A ASYNC MEMORY BANK 3 (1M BYTE) M ASYNC MEMORY BANK 3 (1M BYTE) M Y 0x2030 0000 0x2030 0000 Y R R ASYNC MEMORY BANK 2 (1M BYTE) O ASYNC MEMORY BANK 2 (1M BYTE) O 0x2020 0000 M E 0x2020 0000 M E ASYNC MEMORY BANK 1 (1M BYTE) M ASYNC MEMORY BANK 1 (1M BYTE) M 0x2010 0000 L 0x2010 0000 L A ASYNC MEMORY BANK 0 (1M BYTE) A N ASYNC MEMORY BANK 0 (1M BYTE) N 0x2000 0000 R 0x2000 0000 R E E RESERVED T RESERVED T X 0x0800 0000 E X 0x0800 0000 E SDRAM MEMORY (16M BYTE TO 128M BYTE) SDRAM MEMORY (16M BYTE TO 128M BYTE) 0x0000 0000 0x0000 0000
Figure 3. ADSP-BF531 Internal/External Memory Map Figure 5. ADSP-BF533 Internal/External Memory Map
Event Handling 0xFFFF FFFF CORE MMR REGISTERS (2M BYTE) 0xFFE0 0000
The event controller on the processors handle all asynchronous
SYSTEM MMR REGISTERS (2M BYTE)
and synchronous events to the processor. The ADSP-BF531/
0xFFC0 0000 RESERVED
ADSP-BF532/ADSP-BF533 processors provide event handling
0xFFB0 1000
that supports both nesting and prioritization. Nesting allows
SCRATCHPAD SRAM (4K BYTE) 0xFFB0 0000 P
multiple event service routines to be active simultaneously. Pri-
RESERVED A M 0xFFA1 4000
oritization ensures that servicing of a higher priority event takes
Y INSTRUCTION SRAM/CACHE (16K BYTE) R
precedence over servicing of a lower priority event. The control-
O 0xFFA1 0000 M INSTRUCTION SRAM (32K BYTE) E
ler provides support for five different types of events:
M 0xFFA0 8000 L RESERVED A
• Emulation – An emulation event causes the processor to
0xFFA0 0000 N R
enter emulation mode, allowing command and control of
RESERVED E T 0xFF90 8000 IN
the processor via the JTAG interface.
DATA BANK B SRAM/CACHE (16K BYTE) 0xFF90 4000
• Reset – This event resets the processor.
RESERVED 0xFF80 8000
• Nonmaskable Interrupt (NMI) – The NMI event can be
DATA BANK A SRAM/CACHE (16K BYTE) 0xFF80 4000
generated by the software watchdog timer or by the NMI
RESERVED 0xEF00 0000
input signal to the processor. The NMI event is frequently
RESERVED P
used as a power-down indicator to initiate an orderly shut-
0x2040 0000 A ASYNC MEMORY BANK 3 (1M BYTE) M
down of the system.
0x2030 0000 RY ASYNC MEMORY BANK 2 (1M BYTE) O
• Exceptions – Events that occur synchronously to program
0x2020 0000 M E
flow (i.e., the exception is taken before the instruction is
ASYNC MEMORY BANK 1 (1M BYTE) M 0x2010 0000 L A
allowed to complete). Conditions such as data alignment
ASYNC MEMORY BANK 0 (1M BYTE) N 0x2000 0000 R
violations and undefined instructions cause exceptions.
RESERVED TE 0x0800 0000 EX
• Interrupts – Events that occur asynchronously to program
SDRAM MEMORY (16M BYTE TO 128M BYTE) 0x0000 0000
flow. They are caused by input pins, timers, and other peripherals, as well as by an explicit software instruction. Figure 4. ADSP-BF532 Internal/External Memory Map Rev. I | Page 6 of 64 | August 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Port General-Purpose I/O Port F Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing General-Purpose I/O Port F Pin Cycle Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 160-Ball CSP_BGA Ball Assignment 169-Ball PBGA Ball Assignment 176-Lead LQFP Pinout Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide