Datasheet ADSP-BF539, ADSP-BF539F (Analog Devices) - 10

ADSP-BF539/ ADSP-BF539F
an external clock input to the PF1 pin (TACLK), an external
SERIAL PERIPHERAL INTERFACE (SPI) PORTS
clock input to the PPI_CLK pin (TMRCLK), or to the internal The processors incorporate three SPI-compatible ports that SCLK. enable the processor to communicate with multiple SPI com- The timer units can be used in conjunction with UART0 to patible devices. measure the width of the pulses in the data stream to provide an The SPI interface uses three pins for transferring data: two data auto-baud detect function for a serial channel. pins (master output-slave input, MOSIx, and master input-slave The timers can generate interrupts to the processor core provid- output, MISOx) and a clock pin (serial clock, SCKx). An SPI ing periodic events for synchronization, either to the system chip select input pin (SPIxSS) lets other SPI devices select the clock or to a count of external signals. processor. For SPI0, seven SPI chip select output pins (SPI0- In addition to the three general-purpose programmable timers, SEL7–1) let the processor select other SPI devices. SPI1 and a fourth timer is also provided. This extra timer is clocked by the SPI2 each have a single SPI chip select output pin (SPI1SEL1 internal processor clock and is typically used as a system tick and SPI2SEL1) for SPI point-to-point communication. Each of clock for generation of operating system periodic interrupts. the SPI select pins is a reconfigured GPIO pin. Using these pins, the SPI ports provide a full-duplex, synchronous serial interface,
SERIAL PORTS (SPORTS)
which supports both master/slave modes and multimaster The ADSP-BF539/ADSP-BF539F processors incorporate four environments. dual-channel synchronous serial ports for serial and multipro- The SPI ports’ baud rate and clock phase/polarities are pro- cessor communications. The SPORTs support the following grammable, and they each have an integrated DMA controller, features: configurable to support transmit or receive data streams. Each • I2S capable operation. SPI DMA controller can only service unidirectional accesses at any given time. • Bidirectional operation – Each SPORT has two sets of inde- pendent transmit and receive pins, enabling 16 channels of The SPI port clock rate is calculated as: I2S stereo audio. f SPI Clock Rate SCLK = ------------------ • Buffered (8-deep) transmit and receive ports – Each port 2  SPIx_BAUD has a data register for transferring data words to and from where the 16-bit SPIx_BAUD register contains a value of 2 to other processor components and shift registers for shifting 65,535. data in and out of the data registers. During transfers, the SPI port simultaneously transmits and • Clocking – Each transmit and receive port can either use an receives by serially shifting data in and out on its two serial data external serial clock or generate its own, in frequencies lines. The serial clock line synchronizes the shifting and sam- ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz. pling of data on the two serial data lines. • Word length – Each SPORT supports serial data words
2-WIRE INTERFACE
from 3 bits to 32 bits in length, transferred most significant bit first or least significant bit first. The processors incorporate two 2-wire interface (TWI) modules that are compatible with the Philips Inter-IC bus standard. The • Framing – Each transmit and receive port can run with or TWI modules offer the capabilities of simultaneous master and without frame sync signals for each data word. Frame sync slave operation, support for 7-bit addressing, and multimedia signals can be generated internally or externally, active high data arbitration. The TWI also includes master clock synchroni- or low, and with either of two pulse widths and early or late zation and support for clock low extension. frame sync. The TWI interface uses two pins for transferring clock (SCLx) • Companding in hardware – Each SPORT can perform and data (SDAx) and supports the protocol at speeds up to A-law or μ-law companding according to ITU recommen- 400 kbps. dation G.711. Companding can be selected on the transmit and/or receive channel of the SPORT without additional The TWI interface pins are compatible with 5 V logic levels. latencies.
UART PORTS
• DMA operations with single-cycle overhead – Each SPORT can automatically receive and transmit multiple buffers of The processors incorporate three full-duplex universal asyn- memory data. The processor can link or chain sequences of chronous receiver/transmitter (UART) ports, which are fully DMA transfers between a SPORT and memory. compatible with PC standard UARTs. The UART ports provide a simplified UART interface to other peripherals or hosts, sup- • Interrupts – Each transmit and receive port generates an porting full-duplex, DMA supported, asynchronous transfers of interrupt upon completing the transfer of a data word or serial data. The UART ports include support for 5 data bits to after transferring an entire data buffer or buffers through 8 data bits, 1 stop bit or 2 stop bits, and none, even, or odd par- DMA. ity. The UART ports support two modes of operation: • Multichannel capability – Each SPORT supports 128 chan- nels out of a 1024-channel window and is compatible with the H.100, H.110, MVIP-90, and HMVIP standards. Rev. F | Page 10 of 60 | October 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration ADSP-BF539/ADSP-BF539F Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory Flash Memory (ADSP-BF539F Only) Flash Memory Programming Flash Memory Sector Protection I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports 2-Wire Interface UART Ports Programmable I/O Pins Programmable Flags (GPIO Port F) General-Purpose I/O Ports C, D, and E Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Controller Area Network (CAN) Interface Media Transceiver MAC layer (MXVR) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Example Connections and Layout Considerations MXVR Board Layout Guidelines Voltage Regulator Layout Guidelines Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Ports Timing Serial Peripheral Interface Ports—Master Timing Serial Peripheral Interface Ports—Slave Timing General-Purpose Port Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing MXVR Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 316-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Ordering Guide