Datasheet ADSP-BF539, ADSP-BF539F (Analog Devices) - 3

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ADSP-BF539/ ADSP-BF539F GENERAL DESCRIPTION
The ADSP-BF539/ADSP-BF539F processors are members of
SYSTEM INTEGRATION
the Blackfin® family of products, incorporating the Analog The ADSP-BF539/ADSP-BF539F processors are highly inte- Devices, Inc./Intel Micro Signal Architecture (MSA). Blackfin grated system-on-a-chip solutions for the next generation of processors combine a dual-MAC, state-of-the-art signal pro- industrial and automotive applications including audio and cessing engine, the advantages of a clean, orthogonal RISC-like video signal processing. By combining advanced memory con- microprocessor instruction set, and single-instruction, multi- figurations, such as on-chip flash memory, with industry- ple-data (SIMD) multimedia capabilities into a single standard interfaces with a high performance signal processing instruction set architecture. core, users can develop cost-effective solutions quickly without The ADSP-BF539/ADSP-BF539F processors are completely the need for costly external components. The system peripherals code compatible with other Blackfin processors, differing only include a MOST Network Media Transceiver (MXVR), three with respect to performance, peripherals, and on-chip memory. UART ports, three SPI ports, four serial ports (SPORT), one These features are shown in Table 1. CAN interface, two 2-wire interfaces (TWI), four general-pur- By integrating a rich set of industry-leading system peripherals pose timers (three with PWM capability), a real-time clock, a and memory, Blackfin processors are the platform of choice for watchdog timer, a parallel peripheral interface, general-purpose next generation applications that require RISC-like program- I/O, and general-purpose flag pins. mability, multimedia support, and leading edge signal
ADSP-BF539/ADSP-BF539F PROCESSOR
processing in one integrated package.
PERIPHERALS Table 1. Processor Features
The ADSP-BF539/ADSP-BF539F processors contain a rich set of peripherals connected to the core via several high bandwidth
Feature ADSP-BF539 ADSP-BF539F8
buses, providing flexibility in system configuration as well as SPORTs 4 4 excellent overall system performance (see Figure 1 on Page 1). UARTs 3 3 The general-purpose peripherals include functions such as UART, timers with PWM (pulse-width modulation) and pulse SPI 3 3 measurement capability, general-purpose flag I/O pins, a real- TWI 2 2 time clock, and a watchdog timer. This set of functions satisfies CAN 1 1 a wide variety of typical system support needs and is augmented MXVR 1 1 by the system expansion capabilities of the device. In addition to these general-purpose peripherals, the processors contain high PPI 1 1 speed serial and parallel ports for interfacing to a variety of Internal 8M bit — 1 audio, video, and modem codec functions. An MXVR trans- Parallel Flash ceiver transmits and receives audio and video data and control Instruction 16K bytes 16K bytes information on a MOST automotive multimedia network. A SRAM/Cache CAN 2.0B controller is provided for automotive control net- works. An interrupt controller manages interrupts from the on- Instruction SRAM 64K bytes 64K bytes chip peripherals or external sources. And power management Data SRAM/Cache 32K bytes 32K bytes control functions tailor the performance and power characteris- Data SRAM 32K bytes 32K bytes tics of the processor and system to many application scenarios. Scratchpad 4K bytes 4K bytes All of the peripherals, GPIO, CAN, TWI, real-time clock, and Maximum 533 MHz 533 MHz timers, are supported by a flexible DMA structure. There are Frequency 1066 MMACS 1066 MMACS also four separate memory DMA channels dedicated to data transfers between the processor’s various memory spaces, Package Option BC-316 BC-316 including external SDRAM and asynchronous memory. Multi-
LOW POWER ARCHITECTURE
ple on-chip buses running at up to 133 MHz provide enough bandwidth to keep the processor core running along with activ- Blackfin processors provide world class power management and ity on all of the on-chip and external peripherals. performance. Blackfin processors are designed in a low power The ADSP-BF539/ADSP-BF539F processors include an on-chip and low voltage design methodology and feature dynamic voltage regulator in support of the processor’s dynamic power power management, the ability to vary both the voltage and fre- management capability. The voltage regulator provides a range quency of operation to significantly lower overall power of core voltage levels from V . The voltage regulator can be consumption. Varying the voltage and frequency can result in a DDEXT bypassed at the user's discretion. substantial reduction in power consumption, compared with simply varying the frequency of operation. This translates into longer battery life and lower heat dissipation. Rev. F | Page 3 of 60 | October 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration ADSP-BF539/ADSP-BF539F Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory Flash Memory (ADSP-BF539F Only) Flash Memory Programming Flash Memory Sector Protection I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports 2-Wire Interface UART Ports Programmable I/O Pins Programmable Flags (GPIO Port F) General-Purpose I/O Ports C, D, and E Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Controller Area Network (CAN) Interface Media Transceiver MAC layer (MXVR) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Example Connections and Layout Considerations MXVR Board Layout Guidelines Voltage Regulator Layout Guidelines Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Ports Timing Serial Peripheral Interface Ports—Master Timing Serial Peripheral Interface Ports—Slave Timing General-Purpose Port Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing MXVR Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 316-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Ordering Guide