Datasheet ADSP-BF592 (Analog Devices) - 9

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ADSP-BF592
Note that when a GPIO pin is used to trigger wake from deep sleep, the programmed wake level must linger for at least 10ns Power Savings Factor to guarantee detection. fCCLKRED V   2   = ---------- DDINTRED  T ------------ RED  ------
Hibernate State—Maximum Static Power Savings
f     CCLKNOM VDDINTNOM TNOM The hibernate state maximizes static power savings by disabling clocks to the processor core (CCLK) and to all of the peripherals % Power Savings = 1 – Power Savings Factor  100% (SCLK), as well as signaling an external voltage regulator that VDDINT can be shut off. Any critical information stored inter- nally (for example, memory contents, register contents, and where: other information) must be written to a nonvolatile storage f device prior to removing power if the processor state is to be CCLKNOM is the nominal core clock frequency preserved. Writing b#0 to the HIBERNATE bit causes fCCLKRED is the reduced core clock frequency EXT_WAKE to transition low, which can be used to signal an VDDINTNOM is the nominal internal supply voltage external voltage regulator to shut down. VDDINTRED is the reduced internal supply voltage Since VDDEXT can still be supplied in this mode, all of the exter- nal pins three-state, unless otherwise specified. This allows TNOM is the duration running at fCCLKNOM other devices that may be connected to the processor to still TRED is the duration running at fCCLKRED have power applied without drawing unwanted current.
VOLTAGE REGULATION
As long as VDDEXT is applied, the VR_CTL register maintains its state during hibernation. All other internal registers and memo- The ADSP-BF592 processor requires an external voltage regula- ries, however, lose their content in the hibernate state. tor to power the VDDINT domain. To reduce standby power consumption, the external voltage regulator can be signaled
Power Savings
through EXT_WAKE to remove power from the processor core. As shown in Table 3, the processor supports two different This signal is high-true for power-up and may be connected power domains, which maximizes flexibility while maintaining directly to the low-true shut-down input of many common compliance with industry standards and conventions. By isolat- regulators. ing the internal logic of the processor into its own power While in the hibernate state, the external supply, VDDEXT, can domain, separate from other I/O, the processor can take advan- still be applied, eliminating the need for external buffers. The tage of dynamic power management without affecting the other external voltage regulator can be activated from this power- I/O devices. There are no sequencing requirements for the down state by asserting the RESET pin, which then initiates a various power domains, but all domains must be powered boot sequence. EXT_WAKE indicates a wakeup to the external according to the appropriate Specifications table for processor voltage regulator. operating conditions, even if the feature/peripheral is not used. The power good (PG) input signal allows the processor to start only after the internal voltage has reached a chosen level. In this
Table 3. Power Domains
way, the startup time of the external regulator is detected after hibernation. For a complete description of the power-good
Power Domain VDD Range
functionality, refer to the ADSP-BF59x Blackfin Processor Hard- All internal logic and memories VDDINT ware Reference. All other I/O VDDEXT
CLOCK SIGNALS
The dynamic power management feature of the processor The processor can be clocked by an external crystal, a sine wave allows both the processor’s input voltage (VDDINT) and clock fre- input, or a buffered, shaped clock derived from an external quency (fCCLK) to be dynamically controlled. clock oscillator. The power dissipated by a processor is largely a function of its If an external clock is used, it should be a TTL-compatible signal clock frequency and the square of the operating voltage. For and must not be halted, changed, or operated below the speci- example, reducing the clock frequency by 25% results in a 25% fied frequency during normal operation. This signal is reduction in dynamic power dissipation, while reducing the connected to the processor’s CLKIN pin. When an external voltage by 25% reduces dynamic power dissipation by more clock is used, the XTAL pin must be left unconnected. than 40%. Further, these power savings are additive, in that if the clock frequency and supply voltage are both reduced, the Alternatively, because the processor includes an on-chip oscilla- power savings can be dramatic, as shown in the following tor circuit, an external crystal may be used. For fundamental equations. frequency operation, use the circuit shown in Figure 4. A parallel-resonant, fundamental frequency, microprocessor- grade crystal is connected across the CLKIN and XTAL pins. The on-chip resistance between CLKIN and the XTAL pin is in the 500 kΩ range. Further parallel resistors are typically not Rev. B | Page 9 of 44 | July 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Core Memory Architecture Internal (Core-Accessible) Memory L1 Utility ROM Custom ROM (Optional) I/O Memory Space Booting from ROM Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) DMA Controllers Processor Peripherals Watchdog Timer Timers Serial Ports Serial Peripheral Interface (SPI) Ports UART Port Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions ITU-R 656 Mode Descriptions TWI Controller Interface Ports General-Purpose I/O (GPIO) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions ADSP-BF592 Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 64-Lead LFCSP Lead Assignment Outline Dimensions Automotive Products Ordering Guide