Datasheet ADSP-BF592 (Analog Devices)

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Blackfin Embedded Processor ADSP-BF592 FEATURES PERIPHERALS Up to 400 MHz high performance Blackfin processor Four 32-bit timers/counters, three with PWM support Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 2 dual-channel, full-duplex synchronous serial ports (SPORT), 40-bit shifter supporting eight stereo I2S channels RISC-like register and instruction model for ease of 2 serial peripheral interface (SPI) compatible ports programming and compiler-friendly support 1 UART with IrDA support Advanced debug, trace, and performance monitoring Parallel peripheral interface (PPI), supporting ITU-R 656 Accepts a wide range of supply voltages for internal and I/O video data formats operations, see Operating Conditions on Page 16 2-wire interface (TWI) controller Off-chip voltage regulator interface 9 peripheral DMAs 64-lead (9 mm × 9 mm) LFCSP package 2 memory-to-memory DMA channels MEMORY Event handler with 28 interrupt inputs 32 general-purpose I/Os (GPIOs), with programmable 68K bytes of core-accessible memory hysteresis (See Table 1 on Page 3 for L1 and L3 memory size details) Debug/JTAG interface 64K byte L1 instruction ROM On-chip PLL capable of frequency multiplication Flexible booting options from internal L1 ROM and SPI mem- ory or from host devices including SPI, PPI, and UART Memory management unit providing memory protection WATCHDOG TIMER SPORT1 PORT F VOLTAGE REGULATOR INTERFACE JTAG TEST AND EMULATION SPI0 PERIPHERAL TIMER2–0 ACCESS BUS GPIO INTERRUPT
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UART CONTROLLER PPI SPORT0 L1 INSTRUCTION L1 INSTRUCTION L1 DATA PORT G ROM DMA SRAM SRAM CONTROLLER DMA SPI1 ACCESS BUS DCB TWI DEB BOOT ROM
Figure 1. Processor Block Diagram Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
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Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Core Memory Architecture Internal (Core-Accessible) Memory L1 Utility ROM Custom ROM (Optional) I/O Memory Space Booting from ROM Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) DMA Controllers Processor Peripherals Watchdog Timer Timers Serial Ports Serial Peripheral Interface (SPI) Ports UART Port Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions ITU-R 656 Mode Descriptions TWI Controller Interface Ports General-Purpose I/O (GPIO) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions ADSP-BF592 Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 64-Lead LFCSP Lead Assignment Outline Dimensions Automotive Products Ordering Guide