Datasheet ADSP-BF606, ADSP-BF607, ADSP-BF608, ADSP-BF609 (Analog Devices) - 10

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 • A 32-bit threshold block with 16 thresholds, a histogram, • ITU-656 status word error detection and correction for and run-length encoding ITU-656 receive modes and ITU-656 preamble and status • Two 32-bit integral blocks that support regular and diago- word decode. nal integrals • Optional packing and unpacking of data to/from 32 bits • An up- and down-scaling unit with independent scaling from/to 8 bits, 16 bits and 24 bits. If packing/unpacking is ratios for horizontal and vertical components enabled, endianness can be configured to change the order of packing/unpacking of bytes/words. • Input and output formatters for compatibility with many data formats, including Bayer input format • RGB888 can be converted to RGB666 or RGB565 for trans- mit modes. The PVP can form a pipe of all the constituent algorithmic modules and is dynamically reconfigurable to form different • Various de-interleaving/interleaving modes for receiv- pipeline structures. ing/transmitting 4:2:2 YCrCb data. The PVP supports the simultaneous processing of up to four • Configurable LCD data enable (DEN) output available on data streams. The memory pipe stream operates on data Frame Sync 3. received by DMA from any L1, L2, or L3 memory. The three
PROCESSOR SAFETY FEATURES
camera pipe streams operate on a common input received directly from any of the three PPI inputs. Optionally, the PIXC The ADSP-BF60x processor has been designed for functional can convert color data received by the PPI and forward luma safety applications. While the level of safety is mainly domi- values to the PVP’s monochrome engine. Each stream has a nated by the system concept, the following primitives are dedicated DMA output. This preprocessing concept ensures provided by the devices to build a robust safety concept. careful use of available power and bandwidth budgets and frees
Dual Core Supervision
up the processor cores for other tasks. The processor has been implemented as dual-core devices to The PVP provides for direct core MMR access to all control/sta- separate critical tasks to large independency. Software models tus registers. Two hardware interrupts interface to the system support mutual supervision of the cores in symmetrical fashion. event controller. For optimal performance, the PVP allows reg- ister programming through its control DMA interface, as well as
Multi-Parity-Bit-Protected L1 Memories
outputting selected status registers through the status DMA interface. This mechanism enables the PVP to automatically In the processor’s L1 memory space, whether SRAM or cache, process job lists completely independent of the Blackfin cores. each word is protected by multiple parity bits to detect the single event upsets that occur in all RAMs. This applies both to L1
Pixel Compositor (PIXC)
instruction and data memory spaces. The pixel compositor (PIXC) provides image overlays with
ECC-Protected L2 Memories
transparent-color support, alpha blending, and color space con- version capabilities for output to TFT LCDs and NTSC/PAL Error correcting codes (ECC) are used to correct single event video encoders. It provides all of the control to allow two data upsets. The L2 memory is protected with a Single Error Correct- streams from two separate data buffers to be combined, Double Error Detect (SEC-DED) code. By default ECC is blended, and converted into appropriate forms for both LCD enabled, but it can be disabled on a per-bank basis. Single-bit panels and digital video outputs. The main image buffer pro- errors are transparently corrected. Dual-bit errors can issue a vides the basic background image, which is presented in the system event or fault if enabled. ECC protection is fully trans- data stream. The overlay image buffer allows the user to add parent to the user, even if L2 memory is read or written by 8-bit multiple foreground text, graphics, or video objects on top of or 16-bit entities. the main image or video data stream.
CRC-Protected Memories Parallel Peripheral Interface (PPI)
While parity bit and ECC protection mainly protect against ran- The processor provides up to three parallel peripheral interfaces dom soft errors in L1 and L2 memory cells, the CRC engines can (PPIs), supporting data widths up to 24 bits. The PPI supports be used to protect against systematic errors (pointer errors) and direct connection to TFT LCD panels, parallel analog-to-digital static content (instruction code) of L1, L2 and even L3 memo- and digital-to-analog converters, video encoders and decoders, ries (DDR2, LPDDR). The processors feature two CRC engines image sensor modules and other general-purpose peripherals. which are embedded in the memory-to-memory DMA control- lers. CRC check sums can be calculated or compared on the fly The following features are supported in the PPI module: during memory transfers, or one or multiple memory regions • Programmable data length: 8 bits, 10 bits, 12 bits, 14 bits, can be continuously scrubbed by single DMA work unit as per 16 bits, 18 bits, and 24 bits per clock. DMA descriptor chain instructions. The CRC engine also pro- tects data loaded during the boot process. • Various framed, non-framed, and general-purpose operat- ing modes. Frame syncs can be generated internally or can be supplied by an external device. Rev. A | Page 10 of 112 | February 2014 Document Outline Blackfin Dual Core Embedded Processor Features Memory Table Of Contents Revision History General Description Blackfin Processor Core Instruction Set Description Processor Infrastructure DMA Controllers CRC Protection Event Handling Trigger Routing Unit (TRU) Pin Interrupts General-Purpose I/O (GPIO) Pin Multiplexing Memory Architecture Internal (Core-Accessible) Memory Static Memory Controller (SMC) Dynamic Memory Controller (DMC) I/O Memory Space Booting Video Subsystem Video Interconnect (VID) Pipelined Vision Processor (PVP) Pixel Compositor (PIXC) Parallel Peripheral Interface (PPI) Processor Safety Features Dual Core Supervision Multi-Parity-Bit-Protected L1 Memories ECC-Protected L2 Memories CRC-Protected Memories Memory Protection System Protection Watchpoint Protection Dual Watchdog Bandwidth Monitor Signal Watchdogs Up/Down Count Mismatch Detection Fault Management Additional Processor Peripherals Timers 3-Phase PWM Units Link Ports Serial Ports (SPORTs) ACM Interface General-Purpose Counters Serial Peripheral Interface (SPI) Ports UART Ports TWI Controller Interface Removable Storage Interface (RSI) Controller Area Network (CAN) 10/100 Ethernet MAC USB 2.0 On-the-Go Dual-Role Device Controller Power and Clock Management Crystal Oscillator (SYS_XTAL) USB Crystal Oscillator Clock Generation Clock Out/External Clock Power Management Reset Control Unit Voltage Regulation System Debug System Watchpoint Unit System Debug Unit Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-BF60x Detailed Signal Descriptions 349-Ball CSP_BGA Signal Descriptions GP I/O Multiplexing for 349-Ball CSP_BGA ADSP-BF60x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation Processor — Absolute Maximum Ratings ESD Sensitivity Processor — Package Information Timing Specifications Clock and Reset Timing Power-Up Reset Timing Asynchronous Read Asynchronous Flash Read Asynchronous Page Mode Read Synchronous Burst Flash Read Asynchronous Write Asynchronous Flash Write All Accesses Bus Request/Bus Grant DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing Enhanced Parallel Peripheral Interface Timing Link Ports Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Timing General-Purpose Port Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing Pulse Width Modulator (PWM) Timing ADC Controller Module (ACM) Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing CAN Interface Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing RSI Controller Timing 10/100 Ethernet MAC Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions Thermal Diode ADSP-BF60x 349-Ball CSP_BGA Ball Assignments 349-Ball CSP_BGA Ball Assignment (Numerical by Ball Number) 349-Ball CSP_BGA Ball Assignment (Alphabetical by Pin Name) 349-Ball CSP_BGA Ball Configuration Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide