Datasheet ADSP-BF606, ADSP-BF607, ADSP-BF608, ADSP-BF609 (Analog Devices) - 2

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REVISION HISTORY 2/14—Rev. 0 to Rev. A
Corrected the signal names in the following figures: Added the system clock output specification and additional DDR2 SDRAM Clock and Control Cycle Timing . 69 peripheral external clocks in Clock Related Operating Condi- DDR2 SDRAM Controller Input AC Timing . 70 tions on Page 53. These changes affect the following peripheral Mobile DDR SDRAM Clock and Control Cycle Timing . 72 timing sections. Added Figure 29 and updated Table 42 in Enhanced Parallel Enhanced Parallel Peripheral Interface Timing . 74 Peripheral Interface Timing . 74 Link Ports . 78 Corrected the tHSPIDM, tSDSCIM, tSPICLK, tHDSM, and tSPITDM specifications in Serial Peripheral Interface (SPI) Port—Master Serial Ports—External Clock . 80 Timing . 86 Serial Peripheral Interface (SPI) Port—Master Timing . 86 Corrected the tHDSPID specification in Serial Peripheral Interface Serial Peripheral Interface (SPI) Port—Slave Timing . 88 (SPI) Port—Slave Timing . 88 ADC Controller Module (ACM) Timing . 96 Corrected tSRDYSCKM1 in Serial Peripheral Interface (SPI) Port— SPI_RDY Timing . 92 Additional revisions include the following. Revised all parameters in Timer Cycle Timing . 94 Corrected S0SEL and S1SEL in Figure 8 Clock Relationships and Divider Values . 54 Corrected the timing diagram in ADC Controller Module (ACM) Timing . 96 Revised the dynamic and static current tables CCLK Dynamic Current per core (mA, with ASF = 1) . 57 Removed TWI signals in footnote 3 in JTAG Test And Emula- Static Current—IDD_DEEPSLEEP (mA) . 58 tion Port Timing . 101 Corrected the t Added models to Automotive Products . 112 WARE parameter in Asynchronous Page Mode Read . 64 Corrected the timing diagram in Bus Request/Bus Grant . 69 Rev. A | Page 2 of 112 | February 2014 Document Outline Blackfin Dual Core Embedded Processor Features Memory Table Of Contents Revision History General Description Blackfin Processor Core Instruction Set Description Processor Infrastructure DMA Controllers CRC Protection Event Handling Trigger Routing Unit (TRU) Pin Interrupts General-Purpose I/O (GPIO) Pin Multiplexing Memory Architecture Internal (Core-Accessible) Memory Static Memory Controller (SMC) Dynamic Memory Controller (DMC) I/O Memory Space Booting Video Subsystem Video Interconnect (VID) Pipelined Vision Processor (PVP) Pixel Compositor (PIXC) Parallel Peripheral Interface (PPI) Processor Safety Features Dual Core Supervision Multi-Parity-Bit-Protected L1 Memories ECC-Protected L2 Memories CRC-Protected Memories Memory Protection System Protection Watchpoint Protection Dual Watchdog Bandwidth Monitor Signal Watchdogs Up/Down Count Mismatch Detection Fault Management Additional Processor Peripherals Timers 3-Phase PWM Units Link Ports Serial Ports (SPORTs) ACM Interface General-Purpose Counters Serial Peripheral Interface (SPI) Ports UART Ports TWI Controller Interface Removable Storage Interface (RSI) Controller Area Network (CAN) 10/100 Ethernet MAC USB 2.0 On-the-Go Dual-Role Device Controller Power and Clock Management Crystal Oscillator (SYS_XTAL) USB Crystal Oscillator Clock Generation Clock Out/External Clock Power Management Reset Control Unit Voltage Regulation System Debug System Watchpoint Unit System Debug Unit Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-BF60x Detailed Signal Descriptions 349-Ball CSP_BGA Signal Descriptions GP I/O Multiplexing for 349-Ball CSP_BGA ADSP-BF60x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation Processor — Absolute Maximum Ratings ESD Sensitivity Processor — Package Information Timing Specifications Clock and Reset Timing Power-Up Reset Timing Asynchronous Read Asynchronous Flash Read Asynchronous Page Mode Read Synchronous Burst Flash Read Asynchronous Write Asynchronous Flash Write All Accesses Bus Request/Bus Grant DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing Enhanced Parallel Peripheral Interface Timing Link Ports Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Timing General-Purpose Port Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing Pulse Width Modulator (PWM) Timing ADC Controller Module (ACM) Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing CAN Interface Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing RSI Controller Timing 10/100 Ethernet MAC Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions Thermal Diode ADSP-BF60x 349-Ball CSP_BGA Ball Assignments 349-Ball CSP_BGA Ball Assignment (Numerical by Ball Number) 349-Ball CSP_BGA Ball Assignment (Alphabetical by Pin Name) 349-Ball CSP_BGA Ball Configuration Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide