Datasheet LTC1878 (Analog Devices) - 7

LTC1878
U OPERATIO Main Control Loop
BURST comparator trips, causing the internal sleep line to The LTC1878 uses a constant frequency, current mode go high and forces off both power MOSFETs. The ITH pin step-down architecture. Both the main (P-channel is then disconnected from the output of the EA amplifier MOSFET) and synchronous (N-channel MOSFET) switches and parked a diode voltage above ground. are internal. During normal operation, the internal top In sleep mode, both power MOSFETs are held off and a power MOSFET is turned on each cycle when the oscillator majority of the internal circuitry is partially turned off, sets the RS latch, and turned off when the current com- reducing the quiescent current to 10µA. The load current parator, ICOMP, resets the RS latch. The peak inductor is now being supplied solely from the output capacitor. current at which ICOMP resets the RS latch is controlled by When the output voltage drops, the ITH pin reconnects to the voltage on the ITH pin, which is the output of error the output of the EA amplifier and the top MOSFET is again amplifier EA. The VFB pin, described in the Pin Functions turned on and this process repeats. section, allows EA to receive an output feedback voltage from an external resistive divider. When the load current
Short-Circuit Protection
increases, it causes a slight decrease in the feedback When the output is shorted to ground, the frequency of the voltage relative to the 0.8V reference, which in turn, oscillator is reduced to about 80kHz, 1/7 the nominal causes the ITH voltage to increase until the average induc- frequency. This frequency foldback ensures that the tor current matches the new load current. While the top inductor current has ample time to decay, thereby pre- MOSFET is off, the bottom MOSFET is turned on until venting runaway. The oscillator’s frequency will progres- either the inductor current starts to reverse as indicated by sively increase to 550kHz (or the synchronized frequency) the current reversal comparator IRCMP, or the beginning of when V the next clock cycle. FB rises above 0.3V. Comparator OVDET guards against transient overshoots
Frequency Synchronization
>6.25% by turning the main switch off and keeping it off A phase-locked loop (PLL) is available on the LTC1878 to until the fault is removed. allow the internal oscillator to be synchronized to an external source connected to the SYNC/MODE pin. The
Burst Mode Operation
output of the phase detector at the PLL LPF pin operates The LTC1878 is capable of Burst Mode operation in which over a 0V to 2.4V range corresponding to 400kHz to the internal power MOSFETs operate intermittently based 700kHz. When locked, the PLL aligns the turn-on of the top on load demand. To enable Burst Mode operation, simply MOSFET to the rising edge of the synchronizing signal. tie the SYNC/MODE pin to VIN or connect it to a logic high When the LTC1878 is clocked by an external source, Burst (VSYNC/MODE > 1.5V). To disable Burst Mode operation and Mode operation is disabled; the LTC1878 then operates in enable PWM pulse skipping mode, connect the SYNC/ PWM pulse skipping mode. In this mode, when the output MODE pin to GND. In this mode, the efficiency is lower at load is very low, current comparator I light loads, but becomes comparable to Burst Mode COMP may remain tripped for several cycles and force the main switch to stay operation when the output load exceeds 50mA. The ad- off for the same number of cycles. Increasing the output vantage of pulse skipping mode is lower output ripple and load slightly allows constant frequency PWM operation to less interference to audio circuitry. resume. This mode exhibits low output ripple as well as When the converter is in Burst Mode operation, the peak low audio noise and reduced RF interference while provid- current of the inductor is set to approximately 250mA, ing reasonable low current efficiency. even though the voltage at the ITH pin indicates a lower Frequency synchronization is inhibited when the feedback value. The voltage at the ITH pin drops when the inductor’s voltage V average current is greater than the load requirement. As FB is below 0.6V. This prevents the external clock from interfering with the frequency foldback for short- the ITH voltage drops below approximately 0.55V, the circuit protection. 7