LTC1878 UUWUAPPLICATIO S I FOR ATIO optimized to provide stable high performance transient external and internal oscillators. This type of phase detec- response regardless of the output capacitor selected. tor will not lock up on input frequencies close to the har- ESR is a direct function of the volume of the capacitor. monics of the VCO center frequency. The PLL hold-in range ∆ Manufacturers such as Taiyo-Yuden, AVX, Kemet, Sprague fH is equal to the capture range, ∆fH = ∆fC = ±150kHz. and Sanyo should be considered for high performance The output of the phase detector is a pair of complemen- capacitors. The POSCAP solid electrolytic chip capacitor tary current sources charging or discharging the external available from Sanyo is an excellent choice for output bulk filter network on the PLL LPF pin. The relationship capacitors due to its low ESR/size ratio. Once the ESR between the voltage on the PLL LPF pin and operating requirement for COUT has been met, the RMS current frequency is shown in Figure 4. A simplified block diagram rating generally far exceeds the IRIPPLE(P-P) requirement. is shown in Figure 5. When using tantalum capacitors, it is critical that they are 800 surge tested for use in switching power supplies. A good choice is the AVX TPS series of surface mount tantalum, 700 available in case heights ranging from 2mm to 4mm. Other capacitor types include KEMET T510 and T495 series and 600 Sprague 593D and 595D series. Consult the manufacturer for other specific recommendations. 500 Output Voltage Programming 400 OSCILLATOR FREQUENCY (kHz) The output voltage is set by a resistive divider according 300 to the following formula: 0 0.4 0.8 1.2 1.6 2.0 V (V) PLL LPF R2 1878 F04 V = 0 8 . V 1+ OUT (2) R 1 Figure 4. Relationship Between Oscillator Frequency and Voltage at PLL LPF Pin The external resistive divider is connected to the output, allowing remote voltage sensing as shown in Figure 3. RLP PHASE 2.4V CLP 0.8V ≤ V DETECTOR OUT ≤ 6V PLL LPF R2 SYNC/ VFB MODE DIGITAL PHASE/ LTC1878 VCO R1 FREQUENCY GND DETECTOR 1878 F03 Figure 3. Setting the LTC1878 Output VoltagePhase-Locked Loop and Frequency Synchronization 1878 F05 The LTC1878 has an internal voltage-controlled oscillator Figure 5. Phase-Locked Loop Block Diagram and phase detector comprising a phase-locked loop. This allows the top MOSFET turn-on to be locked to the rising If the external frequency (VSYNC/MODE) is greater than edge of an external frequency source. The frequency range 550kHz, the center frequency, current is sourced of the voltage-controlled oscillator is 400kHz to 700kHz. The continuously, pulling up the PLL LPF pin. When the phase detector used is an edge sensitive digital type that external frequency is less than 550kHz, current is sunk provides zero degrees phase shift between the continuously, pulling down the PLL LPF pin. If the 10