Datasheet LTC3447 (Analog Devices) - 10
| Fabricante | Analog Devices |
| Descripción | I2C Controllable Buck Regulator in 3mm × 3mm DFN |
| Páginas / Página | 16 / 10 — OPERATIO. The START and STOP Commands. Acknowledge. Commands Supported. … |
| Formato / tamaño de archivo | PDF / 578 Kb |
| Idioma del documento | Inglés |
OPERATIO. The START and STOP Commands. Acknowledge. Commands Supported. Data Transfer Timing for Write Commands
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LTC3447
U OPERATIO The START and STOP Commands
be left HIGH by the slave. The master can then generate a STOP command to abort the transfer. When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a transmission If a slave receiver does acknowledge the slave address but, with a START command by transitioning SDA from high some time later in the transfer cannot receive any more to low while SCL is high. When the master has fi nished data bytes, the master must again abort the transfer. This communicating with the slave, it issues a STOP command is indicated by the slave generating the not acknowledge by transitioning SDA from low to high while SCL is high. on the fi rst byte to follow. The slave leaves the data line The bus is then free for another transmission. HIGH and the master generates the STOP command. The data line is also left high by the slave and master after a
Acknowledge
slave has transmitted a byte of data to the master in a read The acknowledge signal is used for handshaking between operation, but this is a not acknowledge that indicates that the master and the slave. An acknowledge signal (LOW the data transfer is successful. active) is generated by the slave lets the master know that
Commands Supported
the latest byte of information was received. The acknowl- edge-related clock pulse is generated by the master. The The LTC3447 supports only write byte commands to a transmitter master releases the SDA line (HIGH) during single register. During ACK bit periods, the LTC3447 will the acknowledge clock pulse. The slave receiver must pull pull the data line low to acknowledge the master device. down the SDA line during the acknowledge clock pulse See Figure 7. so that it remains stable LOW during the HIGH period of this clock pulse.
Data Transfer Timing for Write Commands
When a slave receiver doesn’t acknowledge the slave In order to help assure that bad data is not written into address (for example, it’s unable to receive because it’s the part, data from a write command is only stored after performing some real-time function), the data line must a valid STOP command has been performed. WRITE BYTE PROTOCOL 1 7 1 1 8 1 1 START 1100110 0 ACK XXXXXXXX ACK STOP SLAVE WRITE DATA ADDRESS I2C REGISTER DEFINITION MSB 7 6 5 4 3 2 1 0 LSB DISABLE ENABLE BUCK BUCK BUCK BUCK BUCK BUCK BURST PGOOD DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 (DEFAULT = 0) BLANKING (DEFAULT = 1) (DEFAULT = 0)(DEFAULT = 0)(DEFAULT = 0)(DEFAULT = 0) (DEFAULT = 0) (DEFAULT = 0) 3447 F07
Figure 7. LTC3447’s Write I2C Protocol
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U OPERATIO The START and STOP Commands
be left HIGH by the slave. The master can then generate a STOP command to abort the transfer. When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a transmission If a slave receiver does acknowledge the slave address but, with a START command by transitioning SDA from high some time later in the transfer cannot receive any more to low while SCL is high. When the master has fi nished data bytes, the master must again abort the transfer. This communicating with the slave, it issues a STOP command is indicated by the slave generating the not acknowledge by transitioning SDA from low to high while SCL is high. on the fi rst byte to follow. The slave leaves the data line The bus is then free for another transmission. HIGH and the master generates the STOP command. The data line is also left high by the slave and master after a
Acknowledge
slave has transmitted a byte of data to the master in a read The acknowledge signal is used for handshaking between operation, but this is a not acknowledge that indicates that the master and the slave. An acknowledge signal (LOW the data transfer is successful. active) is generated by the slave lets the master know that
Commands Supported
the latest byte of information was received. The acknowl- edge-related clock pulse is generated by the master. The The LTC3447 supports only write byte commands to a transmitter master releases the SDA line (HIGH) during single register. During ACK bit periods, the LTC3447 will the acknowledge clock pulse. The slave receiver must pull pull the data line low to acknowledge the master device. down the SDA line during the acknowledge clock pulse See Figure 7. so that it remains stable LOW during the HIGH period of this clock pulse.
Data Transfer Timing for Write Commands
When a slave receiver doesn’t acknowledge the slave In order to help assure that bad data is not written into address (for example, it’s unable to receive because it’s the part, data from a write command is only stored after performing some real-time function), the data line must a valid STOP command has been performed. WRITE BYTE PROTOCOL 1 7 1 1 8 1 1 START 1100110 0 ACK XXXXXXXX ACK STOP SLAVE WRITE DATA ADDRESS I2C REGISTER DEFINITION MSB 7 6 5 4 3 2 1 0 LSB DISABLE ENABLE BUCK BUCK BUCK BUCK BUCK BUCK BURST PGOOD DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 (DEFAULT = 0) BLANKING (DEFAULT = 1) (DEFAULT = 0)(DEFAULT = 0)(DEFAULT = 0)(DEFAULT = 0) (DEFAULT = 0) (DEFAULT = 0) 3447 F07
Figure 7. LTC3447’s Write I2C Protocol
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