Datasheet LT3510 (Analog Devices) - 10

LT3510
BLOCK DIAGRAM
RT/SYNC V ONE CHANNEL IN CLK1 R3 OSCILLATOR C VIN1 INTERNAL AND CLK2 REGULATOR AGC DROPOUT BST AND ENHANCEMENT REFERENCE 3μA SLOPE 7μA C3 COMPENSATION PRE – S 3 DRIVER Q + CIRCUITRY R SW SHDN + L1 D + – IND SHUTDOWN 1.28V COMPARATOR POR + UNDERVOLTAGE D – TSD VOUT + 0.8V C + R1 LOWEST FB – VOLTAGE V R2 C CLAMP S R Q POWER GOOD 3.25A COMPARATOR PGOOD – – + + + SS CLAMP + SOFT-START 80mV 0.72V GND RESET COMPARATOR 3510 BD SS VC C
Figure 1. Block Diagram (One of Two Switching Regulators Shown) APPLICATIONS INFORMATION
The LT3510 is dual channel, constant frequency, current When the SHDN pin is opened or driven above 1.28V, mode buck converter with internal 2A switches. Each the internal bias circuits turn on generating an internal channel is identical with a common shutdown pin, internal regulated voltage, 0.8VFB, 0.975V RT/SYNC references, regulator, oscillator, undervoltage detect, thermal shutdown and a POR signal which sets the soft-start latch. and power-on reset. As the RT/SYNC pin reaches its 0.975V regulation point, If the SHDN pin is taken below its 1.28V threshold the the internal oscillator will start generating two clock sig- LT3510 will be placed in a low quiescent current mode. nals 180° out of phase for each regulator at a frequency In this mode the LT3510 typically draws 9μA from VIN1 determined by the resistor from the RT/SYNC pin to ground. and <1μA from VIN2. In shutdown mode the PG is active Alternatively, if a synchronization signal is detected by the with a typical sink capability of 50μA for VIN1 voltage LT3510 at the RT/SYNC pin, clock signals 180° out of phase greater than 2V. 3510fe 10 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS BLOCK DIAGRAM APPLICATIONS INFORMATION TYPICAL APPLICATIONS PACKAGE DESCRIPTION REVISION HISTORY RELATED PARTS