Datasheet LT3510 (Analog Devices) - 8
| Fabricante | Analog Devices |
| Descripción | Monolithic Dual Tracking 2A Step-Down Switching Regulator |
| Páginas / Página | 30 / 8 — PIN FUNCTIONS VIN1 (Pin 1):. SS1/SS2 (Pins 19, 12):. VC1/VC2 (Pins 18, … |
| Formato / tamaño de archivo | PDF / 358 Kb |
| Idioma del documento | Inglés |
PIN FUNCTIONS VIN1 (Pin 1):. SS1/SS2 (Pins 19, 12):. VC1/VC2 (Pins 18, 13):. SW1/SW2 (Pins 2, 9):. IND1/IND2 (Pins 3, 8):
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LT3510
PIN FUNCTIONS VIN1 (Pin 1):
The VIN1 pin powers the internal control
SS1/SS2 (Pins 19, 12):
The SS1/2 pins control the soft- circuitry for both channels and is monitored by the start and sequence of their respective outputs. A single undervoltage lockout comparator. The VIN1 pin is also capacitor from the SS pin to ground determines the outpt connected to the collector of channel 1’s on-chip power ramp rate. For soft-start and output tracking/sequencing NPN switch. The VIN1 pin has high dI/dt edges and must details, see the Applications Information section. be decoupled to ground close to the pin of the device.
VC1/VC2 (Pins 18, 13):
The VC pin is the output of the
SW1/SW2 (Pins 2, 9):
The SW pin is the emitter of the on- error amplifi er and the input to the peak switch current chip power NPN. At switch off, the inductor will drive this comparator. It is normally used for frequency compensa- pin below ground with a high dV/dt. An external Schottky tion, but can also be used as a current clamp or control catch diode to ground, close to the SW pin and respective loop override. If the error amplifi er drives VC above the VIN decoupling capacitor’s ground, must be used to prevent maximum switch current level, a voltage clamp activates. this pin from excessive negative voltages. This indicates that the output is overloaded and current is pulled from the SS pin, reducing the regulation point.
IND1/IND2 (Pins 3, 8):
The IND pin is the input to the on-chip sense resistor that measures current fl owing in
FB1/FB2 (Pins 17, 14):
The FB pin is the negative input the inductor. When the current in the resistor exceeds to the error amplifi er. The output switches regulate this the current dictated by the VC pin, the SW latch is held in pin to 0.8V, with respect to the exposed ground pad. Bias reset, disabling the output switch. Bias current fl ows out current fl ows out of the FB pin. of the IND pin when IND is less than 1.6V.
SHDN (Pin 15):
The shutdown pin is used to turn off both
VOUT1/VOUT2 (Pins 4, 7):
The VOUT pin is the output to channels and control circuitry to reduce quiescent current the on-chip sense resistor that measures current fl owing to a typical value of 9μA. The accurate 1.28V threshold and in the inductor. When the current in the resistor exceeds input current hysteresis can be used as an undervoltage the current dictated by the VC pin, the SW latch is held in lockout, preventing the regulator from operating until the reset, disabling the output switch. Bias current fl ows out input voltage has reached a predetermined level. Force of the VOUT pin when VOUT is less than 1.6V. the SHDN pin above its threshold or let it fl oat for normal operation.
PG1/PG2 (Pins 5, 6):
The power good pin is an open-col- lector output that sinks current when the feedback falls
RT/SYNC (Pin 16):
This RT/SYNC pin provides two modes below 90% of its nominal regulating voltage. For VIN1 of setting the constant switch frequency. above 1V, its output state remains true, although during Connecting a resistor from the R shutdown, V T/SYNC pin to ground IN1 undervoltage lockout or thermal shutdown, will set the R its current sink capability is reduced. The PG pins can be T/SYNC pin to a typical value of 0.975V. The resultant switching frequency will be set by the resistor left open circuit or tied together to form a single power value. The minimum value of 15.4k and maximum value of good signal. 133k sets the switching frequency to 1.5MHz and 250kHz
VIN2 (Pin 10):
The VIN2 pin is the collector of channel 2’s respectively. on-chip power NPN switch. This pin is independent of VIN1 Driving the R and may be connected to the same or a separate supply. In T/SYNC pin with an external clock signal will synchronize the switch to the applied frequency. Synchro- either case, high dI/dt edges are present and decoupling nization occurs on the rising edge of the clock signal after to ground must be used close to this pin. 3510fe 8 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS BLOCK DIAGRAM APPLICATIONS INFORMATION TYPICAL APPLICATIONS PACKAGE DESCRIPTION REVISION HISTORY RELATED PARTS
PIN FUNCTIONS VIN1 (Pin 1):
The VIN1 pin powers the internal control
SS1/SS2 (Pins 19, 12):
The SS1/2 pins control the soft- circuitry for both channels and is monitored by the start and sequence of their respective outputs. A single undervoltage lockout comparator. The VIN1 pin is also capacitor from the SS pin to ground determines the outpt connected to the collector of channel 1’s on-chip power ramp rate. For soft-start and output tracking/sequencing NPN switch. The VIN1 pin has high dI/dt edges and must details, see the Applications Information section. be decoupled to ground close to the pin of the device.
VC1/VC2 (Pins 18, 13):
The VC pin is the output of the
SW1/SW2 (Pins 2, 9):
The SW pin is the emitter of the on- error amplifi er and the input to the peak switch current chip power NPN. At switch off, the inductor will drive this comparator. It is normally used for frequency compensa- pin below ground with a high dV/dt. An external Schottky tion, but can also be used as a current clamp or control catch diode to ground, close to the SW pin and respective loop override. If the error amplifi er drives VC above the VIN decoupling capacitor’s ground, must be used to prevent maximum switch current level, a voltage clamp activates. this pin from excessive negative voltages. This indicates that the output is overloaded and current is pulled from the SS pin, reducing the regulation point.
IND1/IND2 (Pins 3, 8):
The IND pin is the input to the on-chip sense resistor that measures current fl owing in
FB1/FB2 (Pins 17, 14):
The FB pin is the negative input the inductor. When the current in the resistor exceeds to the error amplifi er. The output switches regulate this the current dictated by the VC pin, the SW latch is held in pin to 0.8V, with respect to the exposed ground pad. Bias reset, disabling the output switch. Bias current fl ows out current fl ows out of the FB pin. of the IND pin when IND is less than 1.6V.
SHDN (Pin 15):
The shutdown pin is used to turn off both
VOUT1/VOUT2 (Pins 4, 7):
The VOUT pin is the output to channels and control circuitry to reduce quiescent current the on-chip sense resistor that measures current fl owing to a typical value of 9μA. The accurate 1.28V threshold and in the inductor. When the current in the resistor exceeds input current hysteresis can be used as an undervoltage the current dictated by the VC pin, the SW latch is held in lockout, preventing the regulator from operating until the reset, disabling the output switch. Bias current fl ows out input voltage has reached a predetermined level. Force of the VOUT pin when VOUT is less than 1.6V. the SHDN pin above its threshold or let it fl oat for normal operation.
PG1/PG2 (Pins 5, 6):
The power good pin is an open-col- lector output that sinks current when the feedback falls
RT/SYNC (Pin 16):
This RT/SYNC pin provides two modes below 90% of its nominal regulating voltage. For VIN1 of setting the constant switch frequency. above 1V, its output state remains true, although during Connecting a resistor from the R shutdown, V T/SYNC pin to ground IN1 undervoltage lockout or thermal shutdown, will set the R its current sink capability is reduced. The PG pins can be T/SYNC pin to a typical value of 0.975V. The resultant switching frequency will be set by the resistor left open circuit or tied together to form a single power value. The minimum value of 15.4k and maximum value of good signal. 133k sets the switching frequency to 1.5MHz and 250kHz
VIN2 (Pin 10):
The VIN2 pin is the collector of channel 2’s respectively. on-chip power NPN switch. This pin is independent of VIN1 Driving the R and may be connected to the same or a separate supply. In T/SYNC pin with an external clock signal will synchronize the switch to the applied frequency. Synchro- either case, high dI/dt edges are present and decoupling nization occurs on the rising edge of the clock signal after to ground must be used close to this pin. 3510fe 8 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS BLOCK DIAGRAM APPLICATIONS INFORMATION TYPICAL APPLICATIONS PACKAGE DESCRIPTION REVISION HISTORY RELATED PARTS