Datasheet ADP2102 (Analog Devices) - 4

ADP2102 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 2. THERMAL RESISTANCE Parameter Rating
Junction-to-ambient thermal resistance (θJA) of the package is AVIN, EN, MODE, FB/OUT to AGND −0.3 V to +6 V based on modeling and calculation using a 4-layer board. The LX to PGND −0.3 V to (VIN + 0.3 V) junction-to-ambient thermal resistance is highly dependent on PVIN to PGND −0.3 V to +6 V the application and board layout. In applications where high PGND to AGND −0.3 V to +0.3 V maximum power dissipation exists, attention to thermal board AVIN to PVIN −0.3 V to +0.3 V design is required. The value of θJA may vary, depending on PCB Operating Ambient Temperature Range −40°C to +85°C1 material, layout, and environmental conditions. Specified value Junction Temperature Range −40°C to +125°C of θJA is based on a 4-layer, 4 in × 3 in, 2 1/2 oz copper board, Storage Temperature Range −65°C to +150°C as per JEDEC standards. For more information, see the AN-772 Soldering Conditions JEDEC J-STD-020 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). 1 The ADP2102 can be damaged when junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that TJ is within the specified temperature limits. In applications where high power dissipation
Table 3. Thermal Resistance
and poor thermal resistance are present, the maximum ambient temperature
Package Type θJA Unit
may have to be derated. In applications with moderate power dissipation and low PCB thermal resistance, the maximum ambient temperature can 8-Lead LFCSP 54 °C/W exceed the maximum limit as long as the junction temperature is within Maximum Power Dissipation 0.74 W specification limits. The junction temperature (TJ) of the device is dependent on the ambient temperature (T A), the power dissipation of the device (PD), and the junction-to-ambient thermal resistance of the package (θJA). Maximum
BOUNDARY CONDITION
junction temperature (TJ) is calculated from the ambient temperature (TA) and power dissipation (PD) using the formula TJ = TA + (θJA × PD). Unless Natural convection, 4-layer board, exposed pad soldered to PCB. otherwise specified, all other voltages are referenced to AGND. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a
ESD CAUTION
stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. C | Page 4 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE BOUNDARY CONDITION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CONTROL SCHEME CONSTANT ON-TIME TIMER FORCED CONTINUOUS CONDUCTION MODE POWER SAVE MODE SYNCHRONOUS RECTIFICATION CURRENT LIMIT SOFT START ENABLE UNDERVOLTAGE LOCKOUT THERMAL SHUTDOWN APPLICATIONS INFORMATION INDUCTOR SELECTION INPUT CAPACITOR SELECTION OUTPUT CAPACITOR SELECTION TYPICAL APPLICATION CIRCUITS SETTING THE OUTPUT VOLTAGE EFFICIENCY CONSIDERATIONS Power Switch Conduction Losses Inductor Losses Switching Losses Transition Losses THERMAL CONSIDERATIONS DESIGN EXAMPLE Inductor Output Capacitor Input Capacitor Losses CIRCUIT BOARD LAYOUT RECOMMENDATIONS RECOMMENDED LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE