Datasheet LT3695 (Analog Devices) - 9
| Fabricante | Analog Devices |
| Descripción | 1A Fault Tolerant Micropower Step-Down Regulator |
| Páginas / Página | 30 / 9 — PIN FUNCTIONS (LT3695/LT3695-3.3, LT3695-5). PGND (Pin 1, Exposed Pad Pin … |
| Formato / tamaño de archivo | PDF / 508 Kb |
| Idioma del documento | Inglés |
PIN FUNCTIONS (LT3695/LT3695-3.3, LT3695-5). PGND (Pin 1, Exposed Pad Pin 17/Pin 1, Exposed Pad. VIN (Pin 8/Pin 8):. Pin 17):
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LT3695 Series
PIN FUNCTIONS (LT3695/LT3695-3.3, LT3695-5) PGND (Pin 1, Exposed Pad Pin 17/Pin 1, Exposed Pad VIN (Pin 8/Pin 8):
The VIN pin supplies current to the
Pin 17):
This is the power ground used by the catch diode internal regulator and to the internal power switch. This (D1 in the Block Diagram) when its anode is connected to pin must be locally bypassed. the DA pin. The exposed pad may be soldered to the PCB
V
in order to lower the thermal resistance.
C (Pin 9/Pin 9):
The VC pin is the output of the internal error amplifi er. The voltage on this pin controls the peak
DA (Pin 2/Pin 2):
Connect the anode of the catch diode switch current. Tie an RC network from this pin to ground (D1) to this pin. Internal circuitry senses the current to compensate the control loop. through the catch diode providing frequency foldback in
FB (Pin 11) LT3695:
The LT3695 regulates the FB pin to 0.8V. extreme situations. Connect the feedback resistor divider tap to this pin.
NC (Pins 3, 10, 12/Pins 3, 10, 15):
No Connects. These
PG (Pin 13/Pin 11):
The PG pin is the open-collector output pins are not connected to internal circuitry and must be of an internal comparator. PG remains low until the FB pin left fl oating to ensure fault tolerance. (LT3695) or the OUT1,2 pins (LT3695-3.3, LT3695-5) are
SW (Pin 4/Pin 4):
The SW pin is the output of the internal within 10% of the fi nal regulation voltage. PG output is power switch. Connect this pin to the inductor, catch diode valid when VIN is above the minimum input voltage and and boost capacitor. RUN/SS is high.
RUN/SS (Pin 5/Pin 5):
The RUN/SS pin is used to put
GND (Pin 14/Pin 12):
The GND pin is the ground of all the the LT3695 regulators in shutdown mode. Tie to ground internal circuitry. Tie directly to the local GND plane. to shut down the LT3695 regulators. Tie to 2.5V or more
OUT1, OUT2, (Pins 14, 13) LT3695-3.3, LT3695-5:
These for normal operation. RUN/SS also provides a soft-start pins connect to the anode of the boost Schottky diode and function; see the Applications Information section for also supply current to the internal regulator. They also more information. connect to the internal feedback resistors and must be
RT (Pin 6/Pin 6):
Oscillator Resistor Input. Connect a connected to the output. resistor from this pin to ground to set the switching
BD (Pin 15) LT3695:
This pin connects to the anode of frequency. the boost Schottky diode and also supplies current to the
SYNC (Pin 7/Pin 7):
This is the external clock synchroni- LT3695’s internal regulator. zation input. Ground this pin with a 100k resistor for low
BOOST (Pin 16/Pin 16):
This pin is used to provide a ripple Burst Mode operation at low output loads. Tie to drive voltage, higher than the input voltage, to the internal 0.8V or more for pulse-skipping mode operation. Tie to a bipolar NPN power switch. Connect a capacitor (typically clock source for synchronization. Clock edges should have 0.22μF) between BOOST and SW. rise and fall times faster than 1μs. Note that the maximum load current depends on which mode is chosen. See the Applications Information section for more information. 3695fa 9
PIN FUNCTIONS (LT3695/LT3695-3.3, LT3695-5) PGND (Pin 1, Exposed Pad Pin 17/Pin 1, Exposed Pad VIN (Pin 8/Pin 8):
The VIN pin supplies current to the
Pin 17):
This is the power ground used by the catch diode internal regulator and to the internal power switch. This (D1 in the Block Diagram) when its anode is connected to pin must be locally bypassed. the DA pin. The exposed pad may be soldered to the PCB
V
in order to lower the thermal resistance.
C (Pin 9/Pin 9):
The VC pin is the output of the internal error amplifi er. The voltage on this pin controls the peak
DA (Pin 2/Pin 2):
Connect the anode of the catch diode switch current. Tie an RC network from this pin to ground (D1) to this pin. Internal circuitry senses the current to compensate the control loop. through the catch diode providing frequency foldback in
FB (Pin 11) LT3695:
The LT3695 regulates the FB pin to 0.8V. extreme situations. Connect the feedback resistor divider tap to this pin.
NC (Pins 3, 10, 12/Pins 3, 10, 15):
No Connects. These
PG (Pin 13/Pin 11):
The PG pin is the open-collector output pins are not connected to internal circuitry and must be of an internal comparator. PG remains low until the FB pin left fl oating to ensure fault tolerance. (LT3695) or the OUT1,2 pins (LT3695-3.3, LT3695-5) are
SW (Pin 4/Pin 4):
The SW pin is the output of the internal within 10% of the fi nal regulation voltage. PG output is power switch. Connect this pin to the inductor, catch diode valid when VIN is above the minimum input voltage and and boost capacitor. RUN/SS is high.
RUN/SS (Pin 5/Pin 5):
The RUN/SS pin is used to put
GND (Pin 14/Pin 12):
The GND pin is the ground of all the the LT3695 regulators in shutdown mode. Tie to ground internal circuitry. Tie directly to the local GND plane. to shut down the LT3695 regulators. Tie to 2.5V or more
OUT1, OUT2, (Pins 14, 13) LT3695-3.3, LT3695-5:
These for normal operation. RUN/SS also provides a soft-start pins connect to the anode of the boost Schottky diode and function; see the Applications Information section for also supply current to the internal regulator. They also more information. connect to the internal feedback resistors and must be
RT (Pin 6/Pin 6):
Oscillator Resistor Input. Connect a connected to the output. resistor from this pin to ground to set the switching
BD (Pin 15) LT3695:
This pin connects to the anode of frequency. the boost Schottky diode and also supplies current to the
SYNC (Pin 7/Pin 7):
This is the external clock synchroni- LT3695’s internal regulator. zation input. Ground this pin with a 100k resistor for low
BOOST (Pin 16/Pin 16):
This pin is used to provide a ripple Burst Mode operation at low output loads. Tie to drive voltage, higher than the input voltage, to the internal 0.8V or more for pulse-skipping mode operation. Tie to a bipolar NPN power switch. Connect a capacitor (typically clock source for synchronization. Clock edges should have 0.22μF) between BOOST and SW. rise and fall times faster than 1μs. Note that the maximum load current depends on which mode is chosen. See the Applications Information section for more information. 3695fa 9