Datasheet ADP2380 (Analog Devices) - 6

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ADP2380 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PVIN 1 16 BST PVIN 2 15 SW UVLO 3 14 SW ADP2380 PGOOD 4 TOP VIEW 13 LD (Not to Scale) RT 5 12 VREG SYNC 6 11 PGND EN/SS 7 10 GND 8 9 COMP FB NOTES 1. THE EXPOSED PAD SHOULD BE SOLDERED
003
TO A LARGE EXTERNAL COPPER GROUND PLANE UNDERNEATH THE IC FOR THERMAL DISSIPATION.
09939- Figure 3. Pin Configuration (Top View)
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1, 2 PVIN Power Input. Connect PVIN to the input power source and connect a bypass capacitor between this pin and PGND. 3 UVLO Undervoltage Lockout Pin. An external resistor divider can be used to set the turn-on threshold. 4 PGOOD Power-Good Output (Open Drain). It is recommended that a pull-up resistor of 10 kΩ to 100 kΩ be connected to PGOOD. 5 RT Frequency Setting. Connect a resistor between RT and GND to program the switching frequency between 250 kHz and 1.4 MHz. If the RT pin is connected to GND, the switching frequency is set to 290 kHz. If the RT pin is open, the switching frequency is set to 540 kHz. 6 SYNC Synchronization Input. Connect this pin to an external clock to synchronize the switching frequency between 250 kHz and 1.4 MHz (see the Oscillator section and the Synchronization section for details). 7 EN/SS Enable (EN). When this pin voltage falls below 0.5 V, the regulator is disabled. Soft Start (SS). This pin can also be used to set the soft start time. Connect a capacitor from SS to GND to program the slow soft start time. If this pin is open, the regulator is enabled and uses the internal soft start. 8 COMP Error Amplifier Output. Connect an RC network from COMP to FB. 9 FB Feedback Voltage Sense Input. Connect this pin to a resistor divider from VOUT. 10 GND Analog Ground. Connect this pin to the ground plane. 11 PGND Power Ground. Connect this pin to the source of the synchronous N-channel MOSFET. 12 VREG Internal 8 V Regulator Output. Place a 1 µF ceramic capacitor between this pin and GND. 13 LD Low-Side Gate Driver Output. Connect this pin to the gate of the synchronous N-MOSFET. 14, 15 SW Switch Node Output. Connect this pin to the output inductor. 16 BST Supply Rail for the High-Side Gate Drive. Place a 0.1 µF ceramic capacitor between SW and BST. 17 EPAD Exposed Pad. The exposed pad should be soldered to a large external copper ground plane underneath the IC for thermal dissipation. Rev. 0 | Page 6 of 28 Document Outline Features Applications Typical Applications Circuit General Description Revision History Specifications Absolute Maximum Ratings Thermal Information ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Functional Block Diagram Theory of Operation Control Scheme Internal Regulator (VREG) Bootstrap Circuitry Low-Side Driver Oscillator Synchronization Enable and Soft Start Power Good Peak Current-Limit and Short-Circuit Protection Overvoltage Protection (OVP) Undervoltage Lockout (UVLO) Thermal Shutdown Applications Information Input Capacitor Selection Output Voltage Setting Voltage Conversion Limitations Inductor Selection Output Capacitor Selection Low-Side Power Device Selection Programming Input Voltage UVLO Compensation Design Compensation Network Between COMP and GND Compensation Network Between COMP and FB ADIsimPower Design Tool Design Example Output Voltage Setting Frequency Setting Inductor Selection Output Capacitor Selection Low-Side MOSFET Selection Compensation Components Soft Start Time Program Input Capacitor Selection Recommended External Components Circuit Board Layout Recommendations Typical Applications Circuits Outline Dimensions Ordering Guide