Datasheet LT1354 (Analog Devices) - 10

LT1354
U U W U APPLICATIONS INFORMATION
either supply voltage (or the maximum swing if less than
Input Considerations
1/2 supply voltage). Therefore PDMAX is: Each of the LT1354 inputs is the base of an NPN and P a PNP transistor whose base currents are of opposite DMAX = (V+ – V –)(ISMAX) + (V+/2)2/RL polarity and provide first-order bias current cancellation. Example: LT1354CS8 at 70°C, V Because of variation in the matching of NPN and PNP S = ±15V, RL = 100Ω (Note: the minimum short-circuit current at 70°C is beta, the polarity of the input bias current can be positive 24mA, so the output swing is guaranteed only to 2.4V with or negative. The offset current does not depend on 100Ω.) NPN/PNP beta matching and is well controlled. The use of balanced source resistance at each input is recommended PDMAX = (30V • 1.45mA) + (15V–2.4V)(24mA) = 346mW for applications where DC accuracy must be maximized. T The inputs can withstand transient differential input volt- JMAX = 70°C + (346mW • 190°C/W) = 136°C ages up to 10V without damage and need no clamping or
Circuit Operation
source resistance for protection. Differential inputs, how- ever, generate large supply currents (tens of mA) as The LT1354 circuit topology is a true voltage feedback required for high slew rates. If the device is used with amplifier that has the slewing behavior of a current feed- sustained differential inputs, the average supply current back amplifier. The operation of the circuit can be under- will increase, excessive power dissipation will result and stood by referring to the simplified schematic. The inputs the part may be damaged. The part should not be used as are buffered by complementary NPN and PNP emitter a comparator, peak detector or other open-loop applica- followers which drive an 800Ω resistor. The input voltage tion with large, sustained differential inputs. Under appears across the resistor generating currents which are normal, closed-loop operation, an increase of power mirrored into the high impedance node. Complementary dissipation is only noticeable in applications with large followers form an output stage which buffers the gain slewing outputs and is proportional to the magnitude of node from the load. The bandwidth is set by the input the differential input voltage and the percent of the time resistor and the capacitance on the high impedance node. that the inputs are apart. Measure the average supply The slew rate is determined by the current available to current for the application in order to calculate the power charge the gain node capacitance. This current is the dissipation. differential input voltage divided by R1, so the slew rate is proportional to the input. Highest slew rates are there-
Power Dissipation
fore seen in the lowest gain configurations. For example, a 10V output step in a gain of 10 has only a 1V input step, The LT1354 combines high speed and large output drive whereas the same output step in unity gain has a 10 times in a small package. Because of the wide supply voltage greater input step. The curve of Slew Rate vs Input Level range, it is possible to exceed the maximum junction illustrates this relationship. The LT1354 is tested for slew temperature under certain conditions. Maximum junction rate in a gain of –2 so higher slew rates can be expected temperature (TJ) is calculated from the ambient tempera- in gains of 1 and –1, and lower slew rates in higher gain ture (TA) and power dissipation (PD) as follows: configurations. LT1354CN8: TJ = TA + (PD • 130°C/W) The RC network across the output stage is bootstrapped LT1354CS8: TJ = TA + (PD • 190°C/W) when the amplifier is driving a light or moderate load and has no effect under normal operation. When driving a Worst case power dissipation occurs at the maximum capacitive load (or a low value resistive load) the network supply current and when the output voltage is at 1/2 of is incompletely bootstrapped and adds to the compensa- tion at the high impedance node. The added capacitance 10