Datasheet LT5524 (Analog Devices) - 10

LT5524
U U W U APPLICATIO S I FOR ATIO Clipping Free Operation
25 VCC = VCCO = 5V The LT5524 is a class A amplifier. To avoid signal distor- 20 CURRENT VOLTAGE tion, the user must ensure that the LT5524 outputs do not LIMIT LIMIT enter into current or voltage limiting. The following discus- 15 sion applies to maximum gain operation. (dBm) To avoid current clipping, the output signal current should 10 OUT(MAX)P not exceed the DC quiescent current, IOUT = 20mA (typi- cal). Correspondingly, the maximum input voltage, 5 VIN(MAX), is IOUT/gm = 133mV (peak). In power terms, 0 PIN(MAX) = –11.5dBm (assuming RIN = 122Ω). 20 100 1000 2000 ROUT (Ω) To avoid output voltage clipping (due to LT5524 output 5524 F07 stage saturation or breakdown), the single-ended output
Figure 7. Maximum Output Power as a Function of ROUT
voltage swing should stay within the specified limits; i.e., shutdown mode. These inputs are typically coupled by 2V ≤ VOUT ≤ 8V. For a DC output bias of 5V, the maximum means of a capacitor or a transformer to a signal source, single ended swing will be 3Vpeak and the maximum and impedance matching is assumed. In shutdown mode, differential swing will be 6Vpeak. The simultaneous onset the internal bias can handle up to 1µA leakage on the input of both current and voltage limiting occurs when ROUT = coupling capacitors. This reduces the turn-on delay due to 6Vpeak/20mA = 300Ω (typ) for a maximum POUT = the input coupling RC time constant when exiting shut- 17.8dBm. This calculation applies for a sinusoidal signal. down mode. For nonsinusoidal signals, use the appropriate crest fac- tor to calculate the actual maximum power that avoids If DC coupling to the input is required, the external output clipping. common mode bias should track the LT5524’s internal common mode level. The DC current from the LT5524 Although the instantaneous AC voltage on the OUT+ or inputs should not exceed I OUT– pins may in some situations safely exceed 8V (with IN(SINK) = –200µA and IIN(SOURCE) = 400µA. respect to ground), in no case should the DC voltage on these pins be allowed to exceed the ABSMAX tested limit
Stability Considerations
of 7V. The LT5524’s open-loop architecture allows it to drive any For nonoptimal ROUT values, the maximum available out- practical load. Note that LT5524 gain is proportional to the put power will be lower and can be calculated (considering load impedance, and may exceed the reverse isolation at current limiting for ROUT < 300Ω, and voltage limiting for frequencies above 1GHz if the LT5524’s outputs are left ROUT > 300Ω). The result of this calculation is shown in unloaded, with instability as the undesirable consequence. Figure 7. In such cases, placing a resistive differential load (e.g., 4k) The LT5524 input should not be overdriven (P or a small capacitor at the LT5524 outputs can be used to IN > –11.5dBm at maximum gain). The consequences of over- limit the maximum gain. drive are reduced bandwidth and, when the frequency is The LT5524 has about 20GHz gain-bandwidth product. greater than 50MHz, reduced output power. At reduced Hence, attention must be paid to the printed circuit board gain settings, the maximum PIN is increased by an amount layout to avoid output pin to input pin signal coupling (the equal to the gain reduction. evaluation board layout is a good example). Due to the LT5524’s internal power supply regulator, external supply
Input Bias Voltage
decoupling capacitors typically are not required. Likewise, The LT5524 IN+, IN– signal inputs are internally biased to decoupling capacitors on the LT5524 control inputs typi- 1.48V common mode when enabled, and to 1.26V in cally are not needed. Note, however, that the Exposed Pad 5524f 10