Datasheet LT5524 (Analog Devices) - 9
| Fabricante | Analog Devices |
| Descripción | Low Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain |
| Páginas / Página | 16 / 9 — APPLICATIO S I FOR ATIO. Input Interface |
| Formato / tamaño de archivo | PDF / 189 Kb |
| Idioma del documento | Inglés |
APPLICATIO S I FOR ATIO. Input Interface
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LT5524
U U W U APPLICATIO S I FOR ATIO Input Interface
VOSUP C3 For the lowest noise and highest linearity, the LT5524 R1 R2 R LT5524 C1 51 LOAD Ω 51Ω 50 should be driven with a differential input signal. Single- IN+ Ω – ended drive will severely degrade linearity and noise RIN R RLOAD 122Ω OUT C2 50Ω performance. IN– + Example input matching networks are shown in Figures 3 LT5524 F05 and 4.
Figure 5. Output Impedance-Matched and Capacitively Coupled to a Differential Load
Input matching network design criteria are: • DC block the LT5524 internal bias voltage (see Input Note: In Figure 5, (choke) inductors may be placed in Bias Voltage section for DC coupling information) parallel with or used to replace resistors R1 and R2, thus eliminating the DC voltage drop across these resistors. • Match the source impedance to the LT5524, RIN ≅ 122Ω VOSUP • Provide well balanced differential input drive (capacitor C1 RMATCH C2 in Figure 4) 255Ω R LT5524 T2 LOAD IN+ (OPTIONAL) 50 4:1 Ω • Minimize insertion loss to avoid degrading the noise – • • RIN R figure (NF) 122Ω OUT • IN– + LT5524 F06 R1 C1 LT5524 50Ω IN+ –
Figure 6. Output Impedance-Matched and
R
Transformer-Coupled to a Single-Ended Load
R2 IN VSRC C2 122Ω 50Ω IN– + LT5524 F03 Output network design criteria are: • Provide DC isolation between the LT5524 DC output
Figure 3. Input Capacitively-Coupled to a Differential Source
voltage and RLOAD. • Provide a path for the output DC current from the output RSRC T1 LT5524 50Ω 1:2 IN+ voltage source V – OSUP. • • RIN VSRC • 122Ω • Provide an impedance transformation, if required, be- IN– + tween the load impedance, R C2 LT5524 F04 LOAD, and the optimum 0.33µF ROUT loading.
Figure 4. Input Transformer-Coupled to a Single-Ended Source
• Set the bandwidth of the output network. • Optional: Provide board output impedance matching
Output Interface
using resistor RMATCH (when driving a transmission The output interface network provides an impedance line). transformation between the actual load impedance, RLOAD, • Use high linearity passive parts to avoid introducing and the LT5524 output loading, ROUT, chosen to maximize noninearity. power or linearity, or to minimize output noise, or for some other criteria as explained in the following sections. Note that there is a noise penalty of up to 6dB when using power delivered by only one output in Figure 5. Two examples of output matching networks are shown in Figures 5 and 6 (as implemented in the LT5524 demo boards). 5524f 9
U U W U APPLICATIO S I FOR ATIO Input Interface
VOSUP C3 For the lowest noise and highest linearity, the LT5524 R1 R2 R LT5524 C1 51 LOAD Ω 51Ω 50 should be driven with a differential input signal. Single- IN+ Ω – ended drive will severely degrade linearity and noise RIN R RLOAD 122Ω OUT C2 50Ω performance. IN– + Example input matching networks are shown in Figures 3 LT5524 F05 and 4.
Figure 5. Output Impedance-Matched and Capacitively Coupled to a Differential Load
Input matching network design criteria are: • DC block the LT5524 internal bias voltage (see Input Note: In Figure 5, (choke) inductors may be placed in Bias Voltage section for DC coupling information) parallel with or used to replace resistors R1 and R2, thus eliminating the DC voltage drop across these resistors. • Match the source impedance to the LT5524, RIN ≅ 122Ω VOSUP • Provide well balanced differential input drive (capacitor C1 RMATCH C2 in Figure 4) 255Ω R LT5524 T2 LOAD IN+ (OPTIONAL) 50 4:1 Ω • Minimize insertion loss to avoid degrading the noise – • • RIN R figure (NF) 122Ω OUT • IN– + LT5524 F06 R1 C1 LT5524 50Ω IN+ –
Figure 6. Output Impedance-Matched and
R
Transformer-Coupled to a Single-Ended Load
R2 IN VSRC C2 122Ω 50Ω IN– + LT5524 F03 Output network design criteria are: • Provide DC isolation between the LT5524 DC output
Figure 3. Input Capacitively-Coupled to a Differential Source
voltage and RLOAD. • Provide a path for the output DC current from the output RSRC T1 LT5524 50Ω 1:2 IN+ voltage source V – OSUP. • • RIN VSRC • 122Ω • Provide an impedance transformation, if required, be- IN– + tween the load impedance, R C2 LT5524 F04 LOAD, and the optimum 0.33µF ROUT loading.
Figure 4. Input Transformer-Coupled to a Single-Ended Source
• Set the bandwidth of the output network. • Optional: Provide board output impedance matching
Output Interface
using resistor RMATCH (when driving a transmission The output interface network provides an impedance line). transformation between the actual load impedance, RLOAD, • Use high linearity passive parts to avoid introducing and the LT5524 output loading, ROUT, chosen to maximize noninearity. power or linearity, or to minimize output noise, or for some other criteria as explained in the following sections. Note that there is a noise penalty of up to 6dB when using power delivered by only one output in Figure 5. Two examples of output matching networks are shown in Figures 5 and 6 (as implemented in the LT5524 demo boards). 5524f 9