Datasheet LT1676 (Analog Devices) - 6
| Fabricante | Analog Devices |
| Descripción | Wide Input Range, High Efficiency, Step-Down Switching Regulator |
| Páginas / Página | 16 / 6 — BLOCK DIAGRA. OPERATIO. Output Switch Theory |
| Formato / tamaño de archivo | PDF / 149 Kb |
| Idioma del documento | Inglés |
BLOCK DIAGRA. OPERATIO. Output Switch Theory
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LT1676
W BLOCK DIAGRA
VCC 2 5 VIN R1 RSENSE VBG SHDN 1 BIAS VB I Q3 SWDR COMP Q4 Q2 SWDR SWON SYNC 6 OSC LOGIC Q1 BOOST SWOFF 3 VSW D1 GND 4 SWON I BOOST COMP I I VC 8 FB VTH BOOST AMP FB 7 SWOFF gm I Q5 VBG 1676 BD
U OPERATIO
The LT1676 is a current mode switching regulator IC that
Output Switch Theory
has been optimized for high efficiency operation in high One of the classic problems in delivering low output input voltage, low output voltage Buck topologies. The voltage from high input voltage at good efficiency is that Block Diagram shows an overall view of the system. minimizing AC switching losses requires very fast volt- Several of the blocks are straightforward and similar to age (dV/dt) and current (dI/dt) transition at the output those found in traditional designs, including: Internal Bias device. This is in spite of the fact that in a bipolar Regulator, Oscillator and Feedback Amplifier. The novel implementation, slow lateral PNPs must be included in portion includes an elaborate Output Switch section and the switching signal path. Logic Section to provide the control signals required by the switch section. Fast positive-going slew rate action is provided by lateral PNP Q3 driving the Darlington arrangement of Q1 and Q2. The LT1676 operates much the same as traditional The extra β available from Q2 greatly reduces the drive current mode switchers, the major difference being its requirements of Q3. specialized output switch section. Due to space con- straints, this discussion will not reiterate the basics of Although desirable for dynamic reasons, this topology current mode switcher/controllers and the “Buck” topol- alone will yield a large DC forward voltage drop. A second ogy. A good source of information on these topics is lateral PNP, Q4, acts directly on the base of Q1 to reduce Application Note 19. the voltage drop after the slewing phase has taken place. To achieve the desired high slew rate, PNPs Q3 and Q4 are “force-fed” packets of charge via the current sources controlled by the boost signal. 6
W BLOCK DIAGRA
VCC 2 5 VIN R1 RSENSE VBG SHDN 1 BIAS VB I Q3 SWDR COMP Q4 Q2 SWDR SWON SYNC 6 OSC LOGIC Q1 BOOST SWOFF 3 VSW D1 GND 4 SWON I BOOST COMP I I VC 8 FB VTH BOOST AMP FB 7 SWOFF gm I Q5 VBG 1676 BD
U OPERATIO
The LT1676 is a current mode switching regulator IC that
Output Switch Theory
has been optimized for high efficiency operation in high One of the classic problems in delivering low output input voltage, low output voltage Buck topologies. The voltage from high input voltage at good efficiency is that Block Diagram shows an overall view of the system. minimizing AC switching losses requires very fast volt- Several of the blocks are straightforward and similar to age (dV/dt) and current (dI/dt) transition at the output those found in traditional designs, including: Internal Bias device. This is in spite of the fact that in a bipolar Regulator, Oscillator and Feedback Amplifier. The novel implementation, slow lateral PNPs must be included in portion includes an elaborate Output Switch section and the switching signal path. Logic Section to provide the control signals required by the switch section. Fast positive-going slew rate action is provided by lateral PNP Q3 driving the Darlington arrangement of Q1 and Q2. The LT1676 operates much the same as traditional The extra β available from Q2 greatly reduces the drive current mode switchers, the major difference being its requirements of Q3. specialized output switch section. Due to space con- straints, this discussion will not reiterate the basics of Although desirable for dynamic reasons, this topology current mode switcher/controllers and the “Buck” topol- alone will yield a large DC forward voltage drop. A second ogy. A good source of information on these topics is lateral PNP, Q4, acts directly on the base of Q1 to reduce Application Note 19. the voltage drop after the slewing phase has taken place. To achieve the desired high slew rate, PNPs Q3 and Q4 are “force-fed” packets of charge via the current sources controlled by the boost signal. 6