Datasheet LT1676 (Analog Devices) - 10

LT1676
U U W U APPLICATIONS INFORMATION
oscillator frequency during short-circuit conditions can Power loss internal to the LT1676 related to actual output then maintain control with the effective minimum ON time. current is composed of both DC and AC switching losses. These can be roughly estimated as follows: A further potential problem with short-circuit operation might occur if the user were operating the part with its DC switching losses are dominated by output switch “ON oscillator slaved to an external frequency source via the voltage”, i.e., SYNC pin. However, the LT1676 has circuitry that auto- PDC = VON • IOUT • DC matically disables the sync function when the oscillator is slowed down due to abnormally low FB voltage. VON = Output switch ON voltage, typically 1V at 500mA IOUT = Output current
Feedback Divider Considerations
DC = ON duty cycle An LT1676 application typically includes a resistive divider AC switching losses are typically dominated by power lost between V due to the finite rise time and fall time at the V OUT and ground, the center node of which drives SW node. the FB pin to the reference voltage V Assuming, for simplicity, a linear ramp up of both voltage REF. This establishes a fixed ratio between the two resistors, but a second and current and a current rise/fall time equal to 15ns, degree of freedom is offered by the overall impedance PAC = 1/2 • VIN • IOUT • (tr + tf + 30ns) • f level of the resistor pair. The most obvious effect this has is one of efficiency—a higher resistance feedback divider tr = (VIN/1.6)ns in high dV/dt mode will waste less power and offer somewhat higher effi- (VIN/0.16)ns in low dV/dt mode ciency, especially at light load. tf = (VIN/1.6)ns (irrespective of dV/dt mode) f = switching frequency However, remember that oscillator slowdown to achieve short-circuit protection (discussed above) is dependent Total power dissipation of the die is simply the sum of on FB pin behavior, and this in turn, is sensitive to FB node quiescent, DC and AC losses previously calculated. external impedance. Figure 2 shows the typical relation- PD(TOTAL) = PQ + PDC + PAC ship between FB divider Thevenin voltage and impedance, and oscillator frequency. This shows that as feedback
Frequency Compensation
network impedance increases beyond 10k, complete os- Loop frequency compensation is performed by connect- cillator slowdown is not achieved, and short-circuit pro- ing a capacitor, or in most cases a series RC, from the tection may be compromised. And as a practical matter, output of the error amplifier (VC pin) to ground. Proper the product of FB pin bias current and larger FB network loop compensation may be obtained by empirical meth- impedances will cause increasing output voltage error. ods as described in detail in Application Note 19. Briefly, (Nominal cancellation for 10k of FB Thevenin impedance this involves applying a load transient and observing the is included internally.) dynamic response over the expected range of VIN and ILOAD values.
Thermal Considerations
As a practical matter, a second small capacitor, directly Care should be taken to ensure that the worst-case input from the VC pin to ground is generally recommended to voltage and load current conditions do not cause exces- attenuate capacitive coupling from the VSW pin. A typical sive die temperatures. The packages are rated at 110°C/W value for this capacitor is 100pF. (See Switch Node Con- for the 8-pin SO (S8) and 130°C/W for 8-pin PDIP (N8). siderations). Quiescent power is given by:
Switch Node Considerations
PQ = IVIN • VIN + IVCC • VOUT For maximum efficiency, switch rise and fall times are (This assumes that the VCC pin is connected to VOUT.) made as short as practical. To prevent radiation and high 10