Datasheet ADE7758 (Analog Devices) - 9

link to page 33 link to page 12 link to page 18 link to page 18
Data Sheet ADE7758 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS APCF 1 24 DOUT DGND 2 23 SCLK DVDD 3 22 DIN AVDD 4 21 CS IAP 5 ADE7758 20 CLKOUT IAN 6 TOP VIEW 19 CLKIN (Not to Scale) IBP 7 18 IRQ IBN 8 17 VARCF ICP 9 16 VAP ICN 10 15 VBP AGND 11 14 VCP REFIN/OUT 12 13 VN
04443-005 Figure 5. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 APCF Active Power Calibration Frequency (APCF) Logic Output. It provides active power information. This output is used for operational and calibration purposes. The full-scale output frequency can be scaled by writing to the APCFNUM and APCFDEN registers (see the Active Power Frequency Output section). 2 DGND This provides the ground reference for the digital circuitry in the ADE7758, that is, the multiplier, filters, and digital-to-frequency converter. Because the digital return currents in the ADE7758 are small, it is acceptable to connect this pin to the analog ground plane of the whole system. However, high bus capacitance on the DOUT pin can result in noisy digital current that could affect performance. 3 DVDD Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7758. The supply voltage should be maintained at 5 V ± 5% for specified operation. This pin should be decoupled to DGND with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. 4 AVDD Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the ADE7758. The supply should be maintained at 5 V ± 5% for specified operation. Every effort should be made to minimize power supply ripple and noise at this pin by the use of proper decoupling. The Typical Performance Characteristics show the power supply rejection performance. This pin should be decoupled to AGND with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. 5, 6, IAP, IAN, Analog Inputs for Current Channel. This channel is used with the current transducer and is referenced in this 7, 8, IBP, IBN, document as the current channel. These inputs are fully differential voltage inputs with maximum differential 9, 10 ICP, ICN input signal levels of ±0.5 V, ±0.25 V, and ±0.125 V, depending on the gain selections of the internal PGA (see the Analog Inputs section). All inputs have internal ESD protection circuitry. In addition, an overvoltage of ±6 V can be sustained on these inputs without risk of permanent damage. 11 AGND This pin provides the ground reference for the analog circuitry in the ADE7758, that is, ADCs, temperature sensor, and reference. This pin should be tied to the analog ground plane or the quietest ground reference in the system. This quiet ground reference should be used for all analog circuitry, for example, antialiasing filters, current, and voltage transducers. To keep ground noise around the ADE7758 to a minimum, the quiet ground plane should be connected to the digital ground plane at only one point. It is acceptable to place the entire device on the analog ground plane. 12 REFIN/OUT This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 2.4 V ± 8% and a typical temperature coefficient of 30 ppm/°C. An external reference source can also be connected at this pin. In either case, this pin should be decoupled to AGND with a 1 μF ceramic capacitor. 13, 14, VN, VCP, Analog Inputs for the Voltage Channel. This channel is used with the voltage transducer and is referenced as 15, 16 VBP, VAP the voltage channels in this document. These inputs are single-ended voltage inputs with the maximum signal level of ±0.5 V with respect to VN for specified operation. These inputs are voltage inputs with maximum input signal levels of ±0.5 V, ±0.25 V, and ±0.125 V, depending on the gain selections of the internal PGA (see the Analog Inputs section). All inputs have internal ESD protection circuitry, and in addition, an overvoltage of ±6 V can be sustained on these inputs without risk of permanent damage. Rev. E | Page 9 of 72 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS GENERAL DESCRIPTION SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS THEORY OF OPERATION ANTIALIASING FILTER ANALOG INPUTS CURRENT CHANNEL ADC Current Channel Sampling di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR PEAK CURRENT DETECTION Peak Current Detection Using the PEAK Register OVERCURRENT DETECTION INTERRUPT VOLTAGE CHANNEL ADC Voltage Channel Sampling ZERO-CROSSING DETECTION Zero-Crossing Timeout PHASE COMPENSATION PERIOD MEASUREMENT LINE VOLTAGE SAG DETECTION SAG LEVEL SET PEAK VOLTAGE DETECTION Peak Voltage Detection Using the VPEAK Register Overvoltage Detection Interrupt PHASE SEQUENCE DETECTION POWER-SUPPLY MONITOR REFERENCE CIRCUIT TEMPERATURE MEASUREMENT ROOT MEAN SQUARE MEASUREMENT Current RMS Calculation Current RMS Offset Compensation Voltage Channel RMS Calculation Voltage RMS Offset Compensation Voltage RMS Gain Adjust ACTIVE POWER CALCULATION Active Power Gain Calibration Active Power Offset Calibration Sign of Active Power Calculation No-Load Threshold Active Energy Calculation Integration Time Under Steady Load Energy Accumulation Mode Active Power Frequency Output Line Cycle Active Energy Accumulation Mode REACTIVE POWER CALCULATION Reactive Power Gain Calibration Reactive Power Offset Calibration Sign of Reactive Power Calculation Reactive Energy Calculation Integration Time Under Steady Load Energy Accumulation Mode Reactive Power Frequency Output Line Cycle Reactive Energy Accumulation Mode APPARENT POWER CALCULATION Apparent Power Gain Calibration Apparent Power Offset Calibration Apparent Energy Calculation Integration Time Under Steady Load Energy Accumulation Mode Apparent Power Frequency Output Line Cycle Apparent Energy Accumulation Mode ENERGY REGISTERS SCALING WAVEFORM SAMPLING MODE CALIBRATION Calibration Using Pulse Output Gain Calibration Using Pulse Output Example: Watt Gain Calibration of Phase A Using Pulse Output Phase Calibration Using Pulse Output Example: Phase Calibration of Phase A Using Pulse Output Power Offset Calibration Using Pulse Output Example: Offset Calibration of Phase A Using Pulse Output Calibration Using Line Accumulation Gain Calibration Using Line Accumulation Example: Watt Gain Calibration Using Line Accumulation Phase Calibration Using Line Accumulation Example: Phase Calibration Using Line Accumulation Power Offset Calibration Using Line Accumulation Example: Power Offset Calibration Using Line Accumulation Calibration of IRMS and VRMS Offset Example: Calibration of RMS Offsets CHECKSUM REGISTER INTERRUPTS USING THE INTERRUPTS WITH AN MCU INTERRUPT TIMING SERIAL INTERFACE SERIAL WRITE OPERATION SERIAL READ OPERATION ACCESSING THE ON-CHIP REGISTERS REGISTERS COMMUNICATIONS REGISTER OPERATIONAL MODE REGISTER (0x13) MEASUREMENT MODE REGISTER (0x14) WAVEFORM MODE REGISTER (0x15) COMPUTATIONAL MODE REGISTER (0x16) LINE CYCLE ACCUMULATION MODE REGISTER (0x17) INTERRUPT MASK REGISTER (0x18) INTERRUPT STATUS REGISTER (0x19)/RESET INTERRUPT STATUS REGISTER (0x1A) OUTLINE DIMENSIONS ORDERING GUIDE