Datasheet ADE7758 (Analog Devices)

Poly Phase Multifunction Energy Metering IC with Per Phase Information Data Sheet ADE7758 FEATURES Proprietary ADCs and DSP provide high accuracy over large Highly accurate; supports IEC 60687, IEC 61036, IEC 61268, variations in environmental conditions and time IEC 62053-21, IEC 62053-22, and IEC 62053-23 Reference 2.4 V (drift 30 ppm/°C typical) with external Compatible with 3-phase/3-wire, 3-phase/4-wire, and other overdrive capability 3-phase services Single 5 V supply, low power (70 mW typical) Less than 0.1% active energy error over a dynamic range of GENERAL DESCRIPTION 1000 to 1 at 25°C
The ADE7758 is a high accuracy, 3-phase electrical energy
Supplies active/reactive/apparent energy, voltage rms,
measurement IC with a serial interface and two pulse outputs.
current rms, and sampled waveform data
The ADE7758 incorporates second-order Σ-Δ ADCs, a digital
Two pulse outputs, one for active power and the other
integrator, reference circuitry, a temperature sensor, and all the
selectable between reactive and apparent power with
signal processing required to perform active, reactive, and
programmable frequency
apparent energy measurement and rms calculations.
Digital power, phase, and rms offset calibration On-chip, user-programmable thresholds for line voltage SAG
The ADE7758 is suitable to measure active, reactive, and
and overvoltage detections
apparent energy in various 3-phase configurations, such as
An on-chip, digital integrator enables direct interface-to-
WYE or DELTA services, with both three and four wires. The
current sensors with di/dt output
ADE7758 provides system calibration features for each phase,
A PGA in the current channel allows direct interface to
that is, rms offset correction, phase calibration, and power
current transformers
calibration. The APCF logic output gives active power
An SPI®-compatible serial interface with IRQ
information, and the VARCF logic output provides instantaneous reactive or apparent power information.
FUNCTIONAL BLOCK DIAGRAM AVDD REFIN/OUT AGND 4 12 11 |X| ADE7758 POWER SUPPLY AVAG[11:0] MONITOR AVRMSGAIN[11:0] AVRMSOS[11:0] X2 2.4V 4kΩ REACTIVE OR REF APPARENT POWER LPF VARCFNUM[11:0] 90° PHASE AIRMSOS[11:0] PGA1 SHIFTING FILTER IAP 5 + π ADC dt DFC 17 ÷ 2 VARCF IAN 6 – HPF INTEGRATOR LPF2 AVAROS[11:0] AVARG[11:0] VARCFDEN[ 11:0] PGA2 VAP 16 + ADC Φ – PHASE B LPF2 AND PHASE C PGA1 APHCAL[6:0] AWATTOS[11:0] AWG[11:0] DATA IBP 7 + ADC IBN ACTIVE/REACTIVE/AP PARENT ENERGIES 8 – PGA2 AND VOLTAGE/CURRENT RMS CALCUL ATION ACTIVE POWER FOR PHASE B VADIV[7:0] % VBP 15 + (SEE PHASE A FOR DETAILED SIGNAL PATH) APCFNUM[11:0] ADC VARDIV[7:0] % – PGA1 DFC ÷ 1 APCF ICP 9 + WDIV[7:0] % ADC 3 DVDD ICN 10 – ACTIVE/REACTIVE/AP PARENT ENERGIES PGA2 AND VOLTAGE/CURRENT RMS CALCUL ATION APCFDEN[ 11:0] ADE7758 REGISTERS AND 2 DGND VCP 14 + FOR PHASE C SERIAL INTERFACE 19 CLKIN ADC (SEE PHASE A FOR DETAILED SIGNAL PATH) VN 13 – 20 CLKOUT 22 24 23 21 18
43-001
DIN DOUT SCLK CS IRQ
044 Figure 1.
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Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS GENERAL DESCRIPTION SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS THEORY OF OPERATION ANTIALIASING FILTER ANALOG INPUTS CURRENT CHANNEL ADC Current Channel Sampling di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR PEAK CURRENT DETECTION Peak Current Detection Using the PEAK Register OVERCURRENT DETECTION INTERRUPT VOLTAGE CHANNEL ADC Voltage Channel Sampling ZERO-CROSSING DETECTION Zero-Crossing Timeout PHASE COMPENSATION PERIOD MEASUREMENT LINE VOLTAGE SAG DETECTION SAG LEVEL SET PEAK VOLTAGE DETECTION Peak Voltage Detection Using the VPEAK Register Overvoltage Detection Interrupt PHASE SEQUENCE DETECTION POWER-SUPPLY MONITOR REFERENCE CIRCUIT TEMPERATURE MEASUREMENT ROOT MEAN SQUARE MEASUREMENT Current RMS Calculation Current RMS Offset Compensation Voltage Channel RMS Calculation Voltage RMS Offset Compensation Voltage RMS Gain Adjust ACTIVE POWER CALCULATION Active Power Gain Calibration Active Power Offset Calibration Sign of Active Power Calculation No-Load Threshold Active Energy Calculation Integration Time Under Steady Load Energy Accumulation Mode Active Power Frequency Output Line Cycle Active Energy Accumulation Mode REACTIVE POWER CALCULATION Reactive Power Gain Calibration Reactive Power Offset Calibration Sign of Reactive Power Calculation Reactive Energy Calculation Integration Time Under Steady Load Energy Accumulation Mode Reactive Power Frequency Output Line Cycle Reactive Energy Accumulation Mode APPARENT POWER CALCULATION Apparent Power Gain Calibration Apparent Power Offset Calibration Apparent Energy Calculation Integration Time Under Steady Load Energy Accumulation Mode Apparent Power Frequency Output Line Cycle Apparent Energy Accumulation Mode ENERGY REGISTERS SCALING WAVEFORM SAMPLING MODE CALIBRATION Calibration Using Pulse Output Gain Calibration Using Pulse Output Example: Watt Gain Calibration of Phase A Using Pulse Output Phase Calibration Using Pulse Output Example: Phase Calibration of Phase A Using Pulse Output Power Offset Calibration Using Pulse Output Example: Offset Calibration of Phase A Using Pulse Output Calibration Using Line Accumulation Gain Calibration Using Line Accumulation Example: Watt Gain Calibration Using Line Accumulation Phase Calibration Using Line Accumulation Example: Phase Calibration Using Line Accumulation Power Offset Calibration Using Line Accumulation Example: Power Offset Calibration Using Line Accumulation Calibration of IRMS and VRMS Offset Example: Calibration of RMS Offsets CHECKSUM REGISTER INTERRUPTS USING THE INTERRUPTS WITH AN MCU INTERRUPT TIMING SERIAL INTERFACE SERIAL WRITE OPERATION SERIAL READ OPERATION ACCESSING THE ON-CHIP REGISTERS REGISTERS COMMUNICATIONS REGISTER OPERATIONAL MODE REGISTER (0x13) MEASUREMENT MODE REGISTER (0x14) WAVEFORM MODE REGISTER (0x15) COMPUTATIONAL MODE REGISTER (0x16) LINE CYCLE ACCUMULATION MODE REGISTER (0x17) INTERRUPT MASK REGISTER (0x18) INTERRUPT STATUS REGISTER (0x19)/RESET INTERRUPT STATUS REGISTER (0x1A) OUTLINE DIMENSIONS ORDERING GUIDE