Datasheet ADE9078 (Analog Devices) - 10

link to page 25 link to page 25
ADE9078 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Y D A E R D/TNEV X I S O K E Z / / L 1 0 S 4 3 2 1 S O I C F F F F Q Q S M M S C C C C RI RI 0 9 8 7 6 5 4 3 2 1 4 3 3 3 3 3 3 3 3 3 PULL_HIGH 1 30 CLKOUT DGND 2 29 CLKIN DVDDOUT 3 28 GND PM0 4 27 VDD PM1 5 ADE9078 26 AGND RESET 6 TOP VIEW 25 AVDDOUT IAP 7 (Not to Scale) 24 VCP IAN 8 23 VCN IBP 9 22 VBP IBN 10 21 VBN 11 21 31 4 5 1 1 6 7 1 1 81 91 02 P N P N D F 1 2 N P CI CI NI N N E C C A A I G R N N V V F E R NOTES 1. IT IS RECOMMENDED TO TIE THE NC1 AND NC2 PINS TO GROUND. 2. EXPOSED PAD. CREATE A SIMILAR PAD ON THE PRINTED CIRCUIT BOARD (PCB) UNDER THE EXPOSED PAD. SOLDER THE EXPOSED PAD TO THE PAD ON THE PCB TO CONFER MECHANICAL STRENGTH
3
TO THE PACKAGE AND CONNECT ALL GROUNDS
-00
(GND, AGND, DGND, AND REFGND) TOGETHER AT
1 33
THIS POINT.
14 Figure 3. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 PULL_HIGH Pull High. Tie this pin to VDD. 2 DGND Digital Ground. This pin provides the ground reference for the digital circuitry in the ADE9078. Because the digital return currents in the ADE9078 are small, it is acceptable to connect this pin to the analog ground plane of the whole system. Connect all grounds (GND, AGND, DGND, and REFGND) together at one point. 3 DVDDOUT 1.8 V Output of the Digital Low Dropout Regulator (LDO). Decouple this pin with a 0.1 μF ceramic capacitor in parallel with a ceramic 4.7 μF capacitor. 4 PM0 Power Mode Pin 0. PM0, combined with PM1, defines the power mode. For normal operation, PM0 and PM1 must be grounded (see the Power Modes section). 5 PM1 Power Mode Pin 1. PM1 combined with PM0, defines the power mode. For normal operation, PM0 and PM1 must be grounded (see the Power Modes section). 6 RESET Reset Input, Active Low. This pin must stay low for at least 1 μs to trigger a hardware reset. 7, 8 IAP, IAN Analog Inputs, Channel IA. The IAP (positive) and IAN (negative) inputs are fully differential voltage inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4. 9, 10 IBP, IBN Analog Inputs, Channel IB. The IBP (positive) and IBN (negative) inputs are fully differential voltage inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4. 11, 12 ICP, ICN Analog Inputs, Channel IC. The ICP (positive) and ICN (negative) inputs are fully differential voltage inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4. 13, 14 INP, INN Analog Inputs, Channel IN. The INP (positive) and INN (negative) inputs are fully differential voltage inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4. 15 REFGND Ground Reference, Internal Voltage Reference. Connect all grounds (GND, AGND, DGND, and REFGND) together at one point. 16 REF Voltage Reference. The REF pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 1.25 V. An external reference of 1.2 V to 1.25 V can also be connected at this pin. In either case, decouple REF to REFGND with 0.1 μF ceramic capacitor in parallel with a ceramic 4.7 μF capacitor. After reset, the on-chip reference is enabled. To use the internal voltage reference with external circuits, a buffer is required. The full-scale values mentioned in this data sheet are for a voltage reference of 1.25 V. 17 NC1 No Connection. It is recommended to tie this pin to ground. 18 NC2 No Connection. It is recommended to tie this pin to ground. Rev. 0 | Page 10 of 107 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TOTAL ENERGY LINEARITY OVER SUPPLY AND TEMPERATURE FUNDAMENTAL ENERGY LINEARITY WITH FIFTH HARMONIC OVER SUPPLY AND TEMPERATURE TOTAL ENERGY ERROR OVER FREQUENCY RMS LINEARITY OVER TEMPERATURE AND RMS ERROR OVER FREQUENCY ENERGY LINEARITY REPEATABILITY TOTAL ENERGY AND RMS LINEARITY WITH INTEGRATOR ON TOTAL ENERGY ERROR OVER FREQUENCY WITH INTEGRATOR ON TEST CIRCUIT TERMINOLOGY THEORY OF OPERATION ADC Overview Analog Input Configuration Fully Differential Inputs Interfacing to Current and Voltage Sensors Internal RF Immunity Filter Modes of Operation Output Data Rates and Format Voltage Reference CRYSTAL OSCILLATOR/EXTERNAL CLOCK Crystal Selection Load Capacitor Calculation Load Capacitor Calculation Example POWER MANAGEMENT Power Modes Power-On Sequence Brownout Detection Reset Changing to PSM2 or PSM3 MEASUREMENTS (NORMAL MODE) Current Channel Current Channel Measurement Update Rates ADC_REDIRECT Multiplexer Current Channel Gain, xIGAIN IB Calculation Using ICONSEL High-Pass Filter Digital Integrator Phase Compensation Multipoint Gain and Phase Calibration Multipoint Gain and Phase Single-Point Gain and Phase Voltage Channel Voltage Channel Measurements Voltage Channel Gain Energy Measurements Overview Per Phase Energy Measurements Update Rate Power-Based and Filter-Based RMS Measurement Algorithms Filter-Based Total RMS Neutral Current RMS, RMS of Sum of Instantaneous Currents Total Active Power Total Reactive Power Total Apparent Power Fundamental Reactive Power Power Factor Energy Accumulation Signed Energy Accumulation Modes Total Active Energy Accumulation Modes Reactive Energy Accumulation Modes No Load Detection No Load Indications Energy Accumulation Details Internal Energy Register Overflow Rate User Energy Register Update Rate, EGYRDY Reloading or Accumulating User Energy Register User Energy Register Overflow Rate Accessing the User Energy Registers Read User Energy Register with Reset User Energy Register Use Models Digital to Frequency Conversion—CFx Output Energy and Phase Selection Configuring the Maximum CF Pulse Output Frequency Configuring the CF Pulse Width CFx Pulse Sign Clearing the CFx Accumulator Disabling the CFx Pulse Output and CFx Interrupt MEASUREMENTS (PSM1) Overview IRMS, VRMS, and Active Power VAR PSM1 Startup Flow from PSM2 and PSM3 PSM1 Startup Flow from PSM0 Power Accumulation Power Accumulation Details Accessing the User Power Registers Power Sign Detection Zero-Crossing Detection Combined Voltage Zero Crossing Zero-Crossing Output Rates Zero-Crossing Timeout Line Period Calculation Angle Measurement Phase Sequence Error Detection 4-Wire Wye and 4-Wire Delta 3-Wire Delta Peak Detection MEASUREMENTS (PSM2) Overview Low Power Comparator KEY FEATURES FLEXIBLE WAVEFORM BUFFER WITH RESAMPLING MULTIPOINT PHASE/GAIN CALIBRATION RMS OF SUM OF INSTANTANEOUS CURRENTS MEASUREMENT TAMPER MODES POWER FACTOR ZERO-CROSSING TIMEOUT DETECTION LINE PERIOD MEASUREMENT ANGLE MEASUREMENT PHASE SEQUENCE ERROR DETECTION QUICK START APPLICATIONS INFORMATION NON-BLONDEL COMPLIANT METERS APPLYING THE ADE9078 TO A 4-WIRE WYE SERVICE APPLYING THE ADE9078 TO A 3-WIRE DELTA SERVICE APPLYING THE ADE9078 TO A NON-BLONDEL COMPLIANT, 4-WIRE WYE SERVICE APPLYING THE ADE9078 TO A NON-BLONDEL COMPLIANT, 4-WIRE DELTA SERVICE SERVICE TYPE SUMMARY ACCESSING ON-CHIP DATA SPI PROTOCOL OVERVIEW SPI WRITE SPI READ SPI BURST READ SPI PROTOCOL CRC CRC Algorithm ADDITIONAL COMMUNICATION VERIFICATION REGISTERS CRC OF CONFIGURATION REGISTERS CONFIGURATION LOCK WAVEFORM BUFFER FIXED DATA RATE WAVEFORMS Waveform Buffer Filling Indication—Fixed Data Rate Samples FIXED DATA RATE WAVEFORMS FILLING AND TRIGGER-BASED MODES Stop When Buffer Is Full Mode Continuous Fill Mode Stop Filling on Trigger Center Capture Around Trigger Save Event Address and Keep Filling RESAMPLED WAVEFORMS CONFIGURING THE WAVEFORM BUFFER BURST READ WAVEFORM BUFFER SAMPLES FROM SPI Example 1: Fixed Data Rate Data, Seven Channel Samples Example 2: Resampled Data, Phase C (I and V Samples) Example 3: Fixed Data Rate Data, Single Address Read Mode Example 4: Resampled Data, Single Address Read Mode SPI CRC when Reading the Waveform Buffer SPI Last Data Register when Reading the Waveform Buffer INTERRUPTS/EVENTS INTERRUPTS (IRQ0\ AND IRQ1\) EVENT\ STATUS BITS IN ADDITIONAL REGISTERS No Load TROUBLESHOOTING SPI DOES NOT WORK PSM2_CFG REGISTER VALUE IS NOT RETAINED WHEN GOING FROM PSM2 OR PSM3 TO PSM0 REGISTER INFORMATION REGISTER DETAILS OUTLINE DIMENSIONS ORDERING GUIDE