link to page 1 link to page 1 link to page 1 link to page 2 link to page 3 link to page 4 link to page 8 link to page 9 link to page 9 link to page 9 link to page 10 link to page 12 link to page 12 link to page 15 link to page 16 link to page 17 link to page 17 link to page 19 link to page 21 link to page 23 link to page 24 link to page 25 link to page 26 link to page 26 link to page 31 link to page 35 link to page 36 link to page 37 link to page 37 link to page 37 link to page 37 link to page 37 link to page 38 link to page 51 link to page 72 link to page 72 ADE9000Data SheetTABLE OF CONTENTS Features .. 1 Signal-to-Noise Ratio Performance ... 23 Applications ... 1 Test Circuit .. 24 General Description ... 1 Terminology .. 25 Revision History ... 2 Theory of Operation .. 26 Typical Applications Circuit .. 3 Measurements ... 26 Specifications ... 4 Power Quality Measurements ... 31 Timing Characteristics .. 8 Waveform Buffer .. 35 Absolute Maximum Ratings .. 9 Interrupts/Events .. 36 Thermal Resistance .. 9 Accessing On-Chip Data ... 37 ESD Caution .. 9 SPI Protocol Overview .. 37 Pin Configuration and Function Descriptions ... 10 Additional Communication Verification Registers ... 37 Typical Performance Characteristics ... 12 CRC of Configuration Registers... 37 Energy Linearity over Supply and Temperature ... 12 Configuration Lock .. 37 Energy Error over Frequency and Power Factor .. 15 Register Map ... 38 Energy Linearity Repeatability ... 16 Register Details ... 51 RMS Linearity over Temperature and RMS Error over Outline Dimensions ... 72 Frequency .. 17 Ordering Guide .. 72 Energy and RMS Linearity with Integrator On .. 19 Energy and RMS Error over Frequency with Integrator On ... 21 REVISION HISTORY 6/2017—Rev. 0 to Rev. A Changes to General Description .. 1 Change to Operating Temperature Parameter, Table 3 ... 9 Change to Temperature Section ... 34 Change to Waveform Buffer Section .. 35 Change to Address 0x4FE, Table 6 ... 47 1/2017—Revision 0: Initial Version Rev. A | Page 2 of 72 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION REVISION HISTORY TYPICAL APPLICATIONS CIRCUIT SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS ENERGY LINEARITY OVER SUPPLY AND TEMPERATURE ENERGY ERROR OVER FREQUENCY AND POWER FACTOR ENERGY LINEARITY REPEATABILITY RMS LINEARITY OVER TEMPERATURE AND RMS ERROR OVER FREQUENCY ENERGY AND RMS LINEARITY WITH INTEGRATOR ON ENERGY AND RMS ERROR OVER FREQUENCY WITH INTEGRATOR ON SIGNAL-TO-NOISE RATIO PERFORMANCE TEST CIRCUIT TERMINOLOGY THEORY OF OPERATION MEASUREMENTS Current Channel ADC_REDIRECT Multiplexer Current Channel Gain, xIGAIN IB Calculation Using ICONSEL High-Pass Filter Digital Integrator Phase Compensation Multipoint Phase and Gain Calibration Voltage Channel RMS and Power Measurements Total and Fundamental RMS Total and Fundamental Active Power Total and Fundamental Reactive Power Total and Fundamental Apparent Power No Load Detection, Energy Accumulation, and Power Accumulation Features No Load Detection Feature Energy Accumulation Power Accumulation Digital to Frequency Conversion—CFx Output Energy and Phase Selection Configuring the CFx Pulse Width CFx Pulse Sign Clearing the CFx Accumulator POWER QUALITY MEASUREMENTS Zero-Crossing Detection CF3/ZX Zero-Crossing Timeout Line Period Calculation Angle Measurement Phase Sequence Error Detection Fast RMS½ Measurement 10 Cycle RMS/12 Cycle RMS Dip and Swell Indication Overcurrent Indication Peak Detection Power Factor Total Harmonic Distortion (THD) Resampling 128 Points per Cycle Temperature WAVEFORM BUFFER INTERRUPTS/EVENTS ACCESSING ON-CHIP DATA SPI PROTOCOL OVERVIEW ADDITIONAL COMMUNICATION VERIFICATION REGISTERS CRC OF CONFIGURATION REGISTERS CONFIGURATION LOCK REGISTER MAP REGISTER DETAILS OUTLINE DIMENSIONS ORDERING GUIDE