Datasheet ADE9000 (Analog Devices) - 5

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Data Sheet ADE9000 Parameter Min Typ Max Unit Test Conditions/Comments
Fundamental Apparent Energy 0.1 % Over a dynamic range of 5000 to 1, 2 sec accumulation 0.5 % Over a dynamic range of 10,000 to 1, 10 sec accumulation 0.1 % Over a dynamic range of 1000 to 1, 2 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz 0.5 % Over a dynamic range of 5000 to 1, 10 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz IRMS, VRMS 0.1 % Over a dynamic range of 1000 to 1 0.5 % Over a dynamic range of 5000 to 1 0.1 % Over a dynamic range of 500 to 1, PGA = 4, integrator on, HPF corner = 4.98 Hz 0.5 % Over a dynamic range of 1000 to 1, PGA = 4, integrator on, HPF corner = 4.98 Hz Fundamental IRMS, VRMS 0.1 % Over a dynamic range of 1000 to 1 0.5 % Over a dynamic range of 5000 to 1 0.1 % Over a dynamic range of 500 to 1, PGA = 4, integrator on, HPF corner = 4.98 Hz 0.5 % Over a dynamic range of 2000 to 1, PGA = 4, integrator on, HPF corner = 4.98 Hz Active Power, VAR, VA 0.2 % Over a dynamic range of 1000 to 1 0.4 % Over a dynamic range of, 3000 to 1 0.2 % Over a dynamic range of 500 to 1, PGA = 4, integrator on, HPF corner = 4.98 Hz 0.5 % Over a dynamic range of 1000 to 1, PGA = 4, integrator on, HPF corner = 4.98 Hz Power Factor (PF) Error ±0.001 % Over a dynamic range of 5000 to 1 128-Point per Line Cycle Resampled Data 0.1 % An FFT is performed to receive the magnitude response; this error is the worst case error in the magnitude caused by resampling algorithm distortion; input signal is 50 Hz fundamental and ninth harmonic both at half of full scale (FS) −72 dB Amplitude of highest spur; input signal is 50 Hz fundamental and ninth harmonic both at half of FS 1.25 % An FFT is performed to receive the magnitude response; this error is the worst case error in the magnitude caused by resampling algorithm distortion; input signal is 50 Hz fundamental and 31st harmonic, both at half of FS −38 dB Amplitude of highest spur; input signal is 50 Hz fundamental and 31st harmonic, both at half of FS VRMS½, IRMS½ RMS Voltage 0.25 % Data sourced before HPF, no dc offset at Refreshed Each Half-Cycle1 inputs, over a dynamic range of 100 to 1 10 Cycle/12 Cycle IRMS, VRMS1 0.2 % Data sourced before HPF, no dc offset at inputs, over a dynamic range of 100 to 1 Line Period Measurement 0.001 Hz Resolution at 50 Hz Current to Current, Voltage to Voltage, 0.018 Degrees Resolution at 50 Hz and Voltage to Current Angle Measurement Rev. A | Page 5 of 72 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION REVISION HISTORY TYPICAL APPLICATIONS CIRCUIT SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS ENERGY LINEARITY OVER SUPPLY AND TEMPERATURE ENERGY ERROR OVER FREQUENCY AND POWER FACTOR ENERGY LINEARITY REPEATABILITY RMS LINEARITY OVER TEMPERATURE AND RMS ERROR OVER FREQUENCY ENERGY AND RMS LINEARITY WITH INTEGRATOR ON ENERGY AND RMS ERROR OVER FREQUENCY WITH INTEGRATOR ON SIGNAL-TO-NOISE RATIO PERFORMANCE TEST CIRCUIT TERMINOLOGY THEORY OF OPERATION MEASUREMENTS Current Channel ADC_REDIRECT Multiplexer Current Channel Gain, xIGAIN IB Calculation Using ICONSEL High-Pass Filter Digital Integrator Phase Compensation Multipoint Phase and Gain Calibration Voltage Channel RMS and Power Measurements Total and Fundamental RMS Total and Fundamental Active Power Total and Fundamental Reactive Power Total and Fundamental Apparent Power No Load Detection, Energy Accumulation, and Power Accumulation Features No Load Detection Feature Energy Accumulation Power Accumulation Digital to Frequency Conversion—CFx Output Energy and Phase Selection Configuring the CFx Pulse Width CFx Pulse Sign Clearing the CFx Accumulator POWER QUALITY MEASUREMENTS Zero-Crossing Detection CF3/ZX Zero-Crossing Timeout Line Period Calculation Angle Measurement Phase Sequence Error Detection Fast RMS½ Measurement 10 Cycle RMS/12 Cycle RMS Dip and Swell Indication Overcurrent Indication Peak Detection Power Factor Total Harmonic Distortion (THD) Resampling 128 Points per Cycle Temperature WAVEFORM BUFFER INTERRUPTS/EVENTS ACCESSING ON-CHIP DATA SPI PROTOCOL OVERVIEW ADDITIONAL COMMUNICATION VERIFICATION REGISTERS CRC OF CONFIGURATION REGISTERS CONFIGURATION LOCK REGISTER MAP REGISTER DETAILS OUTLINE DIMENSIONS ORDERING GUIDE