Datasheet LTM8032 (Analog Devices) - 7

LTM8032
pin FuncTions VIN (Bank 3):
The VIN pin supplies current to the LTM8032’s
RUN/SS (Pin L5):
Pull RUN/SS pin to less than 0.2V to internal regulator and to the internal power switch. This shut down the LTM8032. Tie to 2.5V or more for normal pin must be locally bypassed with an external, low ESR operation. If the shutdown feature is not used, tie this pin capacitor of at least 2.2µF. to the VIN pin. RUN/SS also provides a soft-start function;
FIN (K3, L3):
Filtered Input. This is the node after the input see the Applications Information section. EMI filter. Use this only if there is a need to modify the
RT (Pin G7):
The RT pin is used to program the switching behavior of the integrated EMI filter or if VIN rises or falls frequency of the LTM8032 by connecting a resistor from rapidly; otherwise, leave these pins unconnected. See the this pin to ground. The Applications Information section of Applications Information section for more details. the data sheet includes a table to determine the resistance
GND (Bank 2):
Tie these GND pins to a local ground plane value based on the desired switching frequency. Minimize below the LTM8032 and the circuit components. In most capacitance at this pin. applications, the bulk of the heat flow out of the LTM8032
SHARE (Pin H7):
Tie this to the SHARE pin of another is through these pads, so the printed circuit design has a LTM8032 when paralleling the outputs. Otherwise, do not large impact on the thermal performance of the part. See connect (leave floating). the PCB Layout and Thermal Considerations sections for
SYNC (Pin L6):
This is the external clock synchronization more details. Return the feedback divider (RADJ) to this net. input. Ground this pin for low ripple Burst Mode® operation
VOUT (Bank 1):
Power Output Pins. Apply the output filter at low output loads. Tie to a stable voltage source greater capacitor and the output load between these pins and than 0.7V to disable Burst Mode operation. Do not leave GND pins. this pin floating. Tie to a clock source for synchronization.
AUX (Pin H5):
Low Current Voltage Source for BIAS. The Clock edges should have rise and fall times faster than 1µs. AUX pin is internally connected to V See synchronization section in Applications Information. OUT and is placed adjacent to the BIAS pin to ease printed circuit board
PGOOD (Pin K7):
The PGOOD pin is the open-collector routing. Although this pin is internally connected to VOUT, output of an internal comparator. PGOOD remains low until
do not
connect this pin to the load. If this pin is not tied the ADJ pin is within 10% of the final regulation voltage. to BIAS, leave it floating. The PGOOD output is valid when VIN is above 3.6V and
BIAS (Pin H4):
The BIAS pin connects to the internal power RUN/SS is high. If this function is not used, leave this bus. Connect to a power source greater than 2.8V. If the pin floating. output is greater than 2.8V, connect this pin to AUX. If
ADJ (Pin J7):
The LTM8032 regulates its ADJ pin to 0.79V. the output voltage is less, connect this to a voltage source Connect the adjust resistor from this pin to ground. The between 2.8V and 25V. Also, make sure that BIAS + VIN value of RADJ is given by the equation: is less than 56V. 196.71 RADJ = VOUT –0.79 where RADJ is in kΩ. 8032fg For more information www.linear.com/LTM8032 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Package Photographs Related Parts