Datasheet LTM8001 (Analog Devices) - 9
| Fabricante | Analog Devices |
| Descripción | 36VIN, 5A μModule Regulator with 5-Output Configurable LDO Array |
| Páginas / Página | 28 / 9 — Typical perForMance characTerisTics. (TA = 25°C unless otherwise noted. … |
| Formato / tamaño de archivo | PDF / 400 Kb |
| Idioma del documento | Inglés |
Typical perForMance characTerisTics. (TA = 25°C unless otherwise noted. Configured per Table 1, where applicable.)
Línea de modelo para esta hoja de datos
Versión de texto del documento
LTM8001
Typical perForMance characTerisTics (TA = 25°C unless otherwise noted. Configured per Table 1, where applicable.) LDO VBIAS Ripple Rejection (VOUT4 = 2.5V, VBIAS45 = 4.5V, VIN45 = 3.5V) LDO Output Ripple
100 90 80 70 1mV/DIV 60 50 40 2µs/DIV 8001 G39 30 VOUT = 1.2V AT 700mA RIPPLE REJECTION (dB) COUT1 = 22µF 20 CSET1 = 1nF VIN = 12V 10 ILOAD = 100mA I V LOAD = 1.1A OUT0 = 1.8V LOADED TO 0 A TOTAL CURRENT OF 5A 10 102 103 104 105 106 100MHz BW FREQUENCY (Hz) 8001 G38
pin FuncTions VIN0 (Bank 1):
The VIN0 bank supplies current to the
BIAS123 (Pin B8):
This pin is the supply pin for the LTM8001’s internal regulator and to the internal power control circuitry of the LDOs connected to VOUT1-VOUT3. switches. This pin must be locally bypassed with an ex- For the LDOs to regulate, this voltage must be more than ternal, low ESR capacitor; see Table 1 for recommended 1.2V to 1.6V greater than the output voltage (see Dropout values. specifications).
GND (Bank 2):
Tie these GND pins to a local ground plane
SS (Pin K4):
The Soft-Start Pin. Place an external capacitor below the LTM8001 and the circuit components. In most to ground to limit the regulated current during start-up applications, the bulk of the heat flow out of the LTM8001 conditions. The soft-start pin has an 11μA charging current. is through these pads, so the printed circuit design has a
SYNC (Pin K7):
Frequency Synchronization Pin. This pin large impact on the thermal performance of the part. See allows the switching frequency to be synchronized to the PCB Layout and Thermal Considerations sections for an external clock. The R more details. Return the feedback divider (R T resistor should be chosen to FB0) to this net. operate the internal clock at 20% slower than the SYNC
VIN45 (Bank 3):
Input to the LDOs connected to VOUT4 and pulse frequency. This pin should be grounded when not VOUT5. It must be locally bypassed with a low ESR capacitor. in use. Do not leave this pin floating. When laying out the
V
board, avoid noise coupling to or from the SYNC trace.
OUT0 (Bank 4):
Switching Power Converter Output Pins. Apply the output filter capacitor and the output load between See the Switching Frequency Synchronization section in these pins and the GND pins. In most cases, an output Applications Information. capacitance made up of a combination of ceramic and elec-
VREF (Pin K8):
Buffered 2V Reference Capable of 0.5mA trolytic capacitors yields the optimal volumetric solution. Drive.
BIAS45 (Pin A8):
This pin is the supply pin for the control
RUN (Pin L4):
The RUN pin acts as an enable pin and circuitry of the LDOs connected to VOUT4 and VOUT5. For turns on the internal circuitry. The pin does not have any the LDOs to regulate, this voltage must be more than pull up or pull down, requiring a voltage bias for normal 1.2V to 1.6V greater than the output voltage (see Dropout part operation. The RUN pin is internally clamped, so it specifications). may be pulled up to a voltage source that is higher than 8001fd For more information www.linear.com/LTM8001 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Package Photo Revision History Typical Application Related Parts
Typical perForMance characTerisTics (TA = 25°C unless otherwise noted. Configured per Table 1, where applicable.) LDO VBIAS Ripple Rejection (VOUT4 = 2.5V, VBIAS45 = 4.5V, VIN45 = 3.5V) LDO Output Ripple
100 90 80 70 1mV/DIV 60 50 40 2µs/DIV 8001 G39 30 VOUT = 1.2V AT 700mA RIPPLE REJECTION (dB) COUT1 = 22µF 20 CSET1 = 1nF VIN = 12V 10 ILOAD = 100mA I V LOAD = 1.1A OUT0 = 1.8V LOADED TO 0 A TOTAL CURRENT OF 5A 10 102 103 104 105 106 100MHz BW FREQUENCY (Hz) 8001 G38
pin FuncTions VIN0 (Bank 1):
The VIN0 bank supplies current to the
BIAS123 (Pin B8):
This pin is the supply pin for the LTM8001’s internal regulator and to the internal power control circuitry of the LDOs connected to VOUT1-VOUT3. switches. This pin must be locally bypassed with an ex- For the LDOs to regulate, this voltage must be more than ternal, low ESR capacitor; see Table 1 for recommended 1.2V to 1.6V greater than the output voltage (see Dropout values. specifications).
GND (Bank 2):
Tie these GND pins to a local ground plane
SS (Pin K4):
The Soft-Start Pin. Place an external capacitor below the LTM8001 and the circuit components. In most to ground to limit the regulated current during start-up applications, the bulk of the heat flow out of the LTM8001 conditions. The soft-start pin has an 11μA charging current. is through these pads, so the printed circuit design has a
SYNC (Pin K7):
Frequency Synchronization Pin. This pin large impact on the thermal performance of the part. See allows the switching frequency to be synchronized to the PCB Layout and Thermal Considerations sections for an external clock. The R more details. Return the feedback divider (R T resistor should be chosen to FB0) to this net. operate the internal clock at 20% slower than the SYNC
VIN45 (Bank 3):
Input to the LDOs connected to VOUT4 and pulse frequency. This pin should be grounded when not VOUT5. It must be locally bypassed with a low ESR capacitor. in use. Do not leave this pin floating. When laying out the
V
board, avoid noise coupling to or from the SYNC trace.
OUT0 (Bank 4):
Switching Power Converter Output Pins. Apply the output filter capacitor and the output load between See the Switching Frequency Synchronization section in these pins and the GND pins. In most cases, an output Applications Information. capacitance made up of a combination of ceramic and elec-
VREF (Pin K8):
Buffered 2V Reference Capable of 0.5mA trolytic capacitors yields the optimal volumetric solution. Drive.
BIAS45 (Pin A8):
This pin is the supply pin for the control
RUN (Pin L4):
The RUN pin acts as an enable pin and circuitry of the LDOs connected to VOUT4 and VOUT5. For turns on the internal circuitry. The pin does not have any the LDOs to regulate, this voltage must be more than pull up or pull down, requiring a voltage bias for normal 1.2V to 1.6V greater than the output voltage (see Dropout part operation. The RUN pin is internally clamped, so it specifications). may be pulled up to a voltage source that is higher than 8001fd For more information www.linear.com/LTM8001 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Package Photo Revision History Typical Application Related Parts