Datasheet ATtiny15L (Atmel) - 6

link to page 54 A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All the different interrupts have a sep- arate Interrupt Vector in the Interrupt Vector table at the beginning of the program memory. The different interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.
The General Purpose
Figure 3 shows the structure of the 32 general purpose registers in the CPU.
Register File Figure 3.
AVR CPU General Purpose Working Registers 7 0 R0 R1 R2 General … Purpose … Working R28 Registers R29 R30 (Z-register Low Byte)R3 R31 (Z-register High Byte) All the register operating instructions in the instruction set have direct- and single-cycle access to all registers. The only exception is the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI, and ORI between a constant and a register and the LDI instruction for load-immediate constant data. These instructions apply to the second half of the registers in the Register File – R16..R31. The general SBC, SUB, CP, AND, OR, and all other operations between two registers or on a single-register apply to the entire Register File. Registers 30 and 31 form a 16-bit pointer (the Z-pointer) which is used for indirect Flash memory and Register File access. When the Register File is accessed, the contents of R31 is discarded by the CPU.
The ALU – Arithmetic
The high-performance AVR ALU operates in direct connection with all the 32 general
Logic Unit
purpose working registers. Within a single clock cycle, ALU operations between regis- ters in the Register File are executed. The ALU operations are divided into three main categories – arithmetic, logic and bit-functions. Some microcontrollers in the AVR prod- uct family feature a hardware multiplier in the arithmetic part of the ALU.
The Flash Program
The ATtiny15L contains 1K byte On-chip, In-System Programmable Flash memory for
Memory
program storage. Since all instructions are single 16-bit words, the Flash is organized as 512 x 16 words. The Flash memory has an endurance of at least 1,000 write/erase cycles. The ATtiny15L Program Counter is nine bits wide, thus addressing the 512 words Flash Program memory. See page 54 for a detailed description on Flash memory programming.
6 ATtiny15L
1187H–AVR–09/07 Document Outline Features Pin Configuration Description Block Diagram Pin Descriptions VCC GND Port B (PB5..PB0) Analog Pins Internal Oscillators ATtiny15L Architectural Overview The General Purpose Register File The ALU - Arithmetic Logic Unit The Flash Program Memory The Program and Data Addressing Modes Register Direct, Single- register Rd Register Indirect Register Direct, Two Registers Rd and Rr I/O Direct Relative Program Addressing, RJMP and RCALL Constant Addressing using the LPM Instruction Subroutine and Interrupt Hardware Stack The EEPROM Data Memory Memory Access and Instruction Execution Timing I/O Memory The Status Register - SREG Reset and Interrupt Handling ATtiny15L Reset Sources Power-on Reset External Reset Brown-out Detection Watchdog Reset MCU Status Register - MCUSR Internal Voltage Reference Voltage Reference Enable Signals and Start-up Time Interrupt Handling Interrupt Response Time The General Interrupt Mask Register - GIMSK The General Interrupt Flag Register - GIFR The Timer/Counter Interrupt Mask Register - TIMSK The Timer/Counter Interrupt Flag Register - TIFR External Interrupt Pin Change Interrupt The MCU Control Register - MCUCR Sleep Modes Idle Mode ADC Noise Reduction Mode Power-down Mode Tuneable Internal RC Oscillator The System Clock Oscillator Calibration Register - OSCCAL Internal PLL for Fast Peripheral Clock Generation Timer/Counters The Timer/Counter0 Prescaler The Timer/Counter1 Prescaler The Special Function IO Register - SFIOR The 8-bit Timer/Counter0 The Timer/Counter0 Control Register - TCCR0 The Timer Counter 0 - TCNT0 The 8-bit Timer/Counter1 The Timer/Counter1 Control Register - TCCR1 The Timer/Counter1 - TCNT1 Timer/Counter1 Output Compare RegisterA - OCR1A Timer/Counter1 in PWM Mode Timer/Counter1 Output Compare RegisterB - OCR1B The Watchdog Timer The Watchdog Timer Control Register - WDTCR EEPROM Read/Write Access The EEPROM Address Register - EEAR The EEPROM Data Register - EEDR The EEPROM Control Register - EECR Preventing EEPROM Corruption The Analog Comparator The Analog Comparator Control and Status Register - ACSR The Analog-to-Digital Converter, Analog Multiplexer, and Gain Stages Features Operation Prescaling and Conversion Timing ADC Noise Canceler Function The ADC Multiplexer Selection Register - ADMUX The ADC Control and Status Register - ADCSR The ADC Data Register - ADCL and ADCH ADLAR = 0 ADLAR = 1 Scanning Multiple Channels ADC Noise-canceling Techniques ADC Characteristics I/O Port B Unconnected Pins Alternative Functions of Port B The Port B Data Register - PORTB The Port B Data Direction Register - DDRB The Port B Input Pins Address - PINB PORT B as General Digital I/O Alternate Functions of Port B Memory Programming Program and Data Memory Lock Bits Fuse Bits Signature Bytes Calibration Byte Programming the Flash High-voltage Serial Programming High-voltage Serial Programming Algorithm High-voltage Serial Programming Characteristics Low-voltage Serial Downloading Low-voltage Serial Programming Algorithm Data Polling Low-voltage Serial Programming Characteristics Electrical Characteristics Absolute Maximum Ratings DC Characteristics Typical Characteristics ATtiny15L Register Summary ATtiny15L Instruction Set Summary Ordering Information Packaging Information 8P3 8S2 Datasheet revision history Rev H - 09/07 Rev G - 06/07 Rev F - 06/05 Table of Contents