Datasheet ATtiny15L (Atmel)

Features
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High-performance, Low-power AVR® 8-bit Microcontroller
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Advanced RISC Architecture – 90 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation
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Non-volatile Program and Data Memories – 1K Byte In-System Programmable Flash Program Memory Endurance: 1,000 Write/Erase Cycles – 64 Bytes EEPROM Endurance: 100,000 Write/Erase Cycles 8-bit – Programming Lock for Flash Program Data Security
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Peripheral Features Microcontroller – Interrupt and Wake-up on Pin Change – Two 8-bit Timer/Counters with Separate Prescalers with 1K Byte – One 150 kHz, 8-bit High-speed PWM Output – 4-channel 10-bit ADC One Differential Voltage Input with Optional Gain of 20x Flash – On-chip Analog Comparator – Programmable Watchdog Timer with On-chip Oscillator
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Special Microcontroller Features – In-System Programmable via SPI Port ATtiny15L – Enhanced Power-on Reset Circuit – Programmable Brown-out Detection Circuit – Internal, Calibrated 1.6 MHz Tunable Oscillator – Internal 25.6 MHz Clock Generator for Timer/Counter – External and Internal Interrupt Sources – Low-power Idle and Power-down Modes
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Power Consumption at 1.6 MHz, 3V, 25
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C – Active: 3.0 mA – Idle Mode: 1.0 mA – Power-down: < 1 µA
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I/O and Packages – 8-lead PDIP and 8-lead SOIC: 6 Programmable I/O Lines
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Operating Voltages – 2.7V - 5.5V
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Internal 1.6 MHz System Clock Pin Configuration
PDIP/SOIC (RESET/ADC0) PB5 1 8 VCC (ADC3) PB4 2 7 PB2 (ADC1/SCK/T0/INT0) (ADC2) PB3 3 6 PB1 (AIN1/MISO/OC1A) GND 4 5 PB0 (AIN0/AREF/MOSI) Not recommended for new design Rev. 1187H–AVR–09/07
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Document Outline Features Pin Configuration Description Block Diagram Pin Descriptions VCC GND Port B (PB5..PB0) Analog Pins Internal Oscillators ATtiny15L Architectural Overview The General Purpose Register File The ALU - Arithmetic Logic Unit The Flash Program Memory The Program and Data Addressing Modes Register Direct, Single- register Rd Register Indirect Register Direct, Two Registers Rd and Rr I/O Direct Relative Program Addressing, RJMP and RCALL Constant Addressing using the LPM Instruction Subroutine and Interrupt Hardware Stack The EEPROM Data Memory Memory Access and Instruction Execution Timing I/O Memory The Status Register - SREG Reset and Interrupt Handling ATtiny15L Reset Sources Power-on Reset External Reset Brown-out Detection Watchdog Reset MCU Status Register - MCUSR Internal Voltage Reference Voltage Reference Enable Signals and Start-up Time Interrupt Handling Interrupt Response Time The General Interrupt Mask Register - GIMSK The General Interrupt Flag Register - GIFR The Timer/Counter Interrupt Mask Register - TIMSK The Timer/Counter Interrupt Flag Register - TIFR External Interrupt Pin Change Interrupt The MCU Control Register - MCUCR Sleep Modes Idle Mode ADC Noise Reduction Mode Power-down Mode Tuneable Internal RC Oscillator The System Clock Oscillator Calibration Register - OSCCAL Internal PLL for Fast Peripheral Clock Generation Timer/Counters The Timer/Counter0 Prescaler The Timer/Counter1 Prescaler The Special Function IO Register - SFIOR The 8-bit Timer/Counter0 The Timer/Counter0 Control Register - TCCR0 The Timer Counter 0 - TCNT0 The 8-bit Timer/Counter1 The Timer/Counter1 Control Register - TCCR1 The Timer/Counter1 - TCNT1 Timer/Counter1 Output Compare RegisterA - OCR1A Timer/Counter1 in PWM Mode Timer/Counter1 Output Compare RegisterB - OCR1B The Watchdog Timer The Watchdog Timer Control Register - WDTCR EEPROM Read/Write Access The EEPROM Address Register - EEAR The EEPROM Data Register - EEDR The EEPROM Control Register - EECR Preventing EEPROM Corruption The Analog Comparator The Analog Comparator Control and Status Register - ACSR The Analog-to-Digital Converter, Analog Multiplexer, and Gain Stages Features Operation Prescaling and Conversion Timing ADC Noise Canceler Function The ADC Multiplexer Selection Register - ADMUX The ADC Control and Status Register - ADCSR The ADC Data Register - ADCL and ADCH ADLAR = 0 ADLAR = 1 Scanning Multiple Channels ADC Noise-canceling Techniques ADC Characteristics I/O Port B Unconnected Pins Alternative Functions of Port B The Port B Data Register - PORTB The Port B Data Direction Register - DDRB The Port B Input Pins Address - PINB PORT B as General Digital I/O Alternate Functions of Port B Memory Programming Program and Data Memory Lock Bits Fuse Bits Signature Bytes Calibration Byte Programming the Flash High-voltage Serial Programming High-voltage Serial Programming Algorithm High-voltage Serial Programming Characteristics Low-voltage Serial Downloading Low-voltage Serial Programming Algorithm Data Polling Low-voltage Serial Programming Characteristics Electrical Characteristics Absolute Maximum Ratings DC Characteristics Typical Characteristics ATtiny15L Register Summary ATtiny15L Instruction Set Summary Ordering Information Packaging Information 8P3 8S2 Datasheet revision history Rev H - 09/07 Rev G - 06/07 Rev F - 06/05 Table of Contents