Datasheet AT90S1200 (Atmel) - 10

I/O Memory
The I/O space definition of the AT90S1200 is shown in the following table.
Table 1.
The AT90S1200 I/O Space
Address Hex Name Function
$3F SREG Status REGister $3B GIMSK General Interrupt MaSK register $39 TIMSK Timer/Counter Interrupt MaSK register $38 TIFR Timer/Counter Interrupt Flag register $35 MCUCR MCU general Control Register $33 TCCR0 Timer/Counter0 Control Register $32 TCNT0 Timer/Counter0 (8-bit) $21 WDTCR Watchdog Timer Control Register $1E EEAR EEPROM Address Register $1D EEDR EEPROM Data Register $1C EECR EEPROM Control Register $18 PORTB Data Register, Port B $17 DDRB Data Direction Register, Port B $16 PINB Input Pins, Port B $12 PORTD Data Register, Port D $11 DDRD Data Direction Register, Port D $10 PIND Input Pins, Port D $08 ACSR Analog Comparator Control and Status Register Note: Reserved and unused locations are not shown in the table. All AT90S1200 I/Os and peripherals are placed in the I/O space. The different I/O loca- tions are accessed by the IN and OUT instructions transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instruc- tions. Refer to the instruction set chapter for more details. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. The different I/O and peripherals control registers are explained in the following sections.
10 AT90S1200
0838H–AVR–03/02 Document Outline Features Pin Configuration Description Block Diagram Pin Descriptions VCC GND Port B (PB7..PB0) Port D (PD6..PD0) RESET XTAL1 XTAL2 Crystal Oscillator On-chip RC Oscillator Architectural Overview General Purpose Register File ALU – Arithmetic Logic Unit In-System Programmable Flash Program Memory Program and Data Addressing Modes Register Direct, Single Register Rd Register Indirect Register Direct, Two Registers Rd and Rr I/O Direct Relative Program Addressing, RJMP and RCALL Subroutine and Interrupt Hardware Stack EEPROM Data Memory Instruction Execution Timing I/O Memory Status Register – SREG Reset and Interrupt Handling Reset Sources Power-on Reset External Reset Watchdog Reset Interrupt Handling General Interrupt Mask Register – GIMSK Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt FLAG Register – TIFR External Interrupts Interrupt Response Time MCU Control Register – MCUCR Sleep Modes Idle Mode Power-down Mode Timer/Counter0 Timer/Counter0 Prescaler Timer/Counter0 Control Register – TCCR0 Timer/Counter0 – TCNT0 Watchdog Timer Watchdog Timer Control Register – WDTCR EEPROM Read/Write Access EEPROM Address Register – EEAR EEPROM Data Register – EEDR EEPROM Control Register – EECR Prevent EEPROM Corruption Analog Comparator Analog Comparator Control and Status Register – ACSR I/O Ports Port B Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pin Address – PINB Port B as General Digital I/O Alternate Functions of Port B Port B Schematics Port D Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND Port D as General Digital I/O Alternate Functions for Port D Port D Schematics Memory Programming Program and Data Memory Lock Bits Fuse Bits Signature Bytes Programming the Flash and EEPROM Parallel Programming Signal Names Enter Programming Mode Chip Erase Programming the Flash Reading the Flash Programming the EEPROM Reading the EEPROM Programming the Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes Parallel Programming Characteristics Serial Downloading Serial Programming Algorithm Data Polling EEPROM Data Polling Flash Serial Programming Characteristics Electrical Characteristics Absolute Maximum Ratings* DC Characteristics External Clock Drive Waveforms External Clock Drive Typical Characteristics AT90S1200 Register Summary Instruction Set Summary Ordering Information(1) Packaging Information 20P3 20S 20Y Table of Contents