Datasheet ATmega644, ATmega644V - Complete (Atmel) - 10

The fast-access Register File contains 32 × 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ- ical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic opera- tion, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word for- mat. Every program memory address contains a 16-bit or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi- tion. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis- ters, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega644 has Extended I/O space from 0x100 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.
5.3 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.
10 ATmega644
2593O–AVR–02/12 Document Outline Features 1. Pin Configurations 1.1 Disclaimer 2. Overview 2.1 Block Diagram 2.2 Pin Descriptions 2.2.1 VCC 2.2.2 GND 2.2.3 Port A (PA7:PA0) 2.2.4 Port B (PB7:PB0) 2.2.5 Port C (PC7:PC0) 2.2.6 Port D (PD7:PD0) 2.2.7 RESET 2.2.8 XTAL1 2.2.9 XTAL2 2.2.10 AVCC 2.2.11 AREF 3. Resources 4. About Code Examples 5. AVR CPU Core 5.1 Introduction 5.2 Architectural Overview 5.3 ALU – Arithmetic Logic Unit 5.4 Status Register 5.4.1 SREG – Status Register 5.5 General Purpose Register File 5.5.1 The X-register, Y-register, and Z-register 5.6 Stack Pointer 5.7 Instruction Execution Timing 5.8 Reset and Interrupt Handling 5.8.1 Interrupt Response Time 6. AVR Memories 6.1 In-System Reprogrammable Flash Program Memory 6.2 SRAM Data Memory 6.2.1 Data Memory Access Times 6.3 EEPROM Data Memory 6.3.1 EEPROM Read/Write Access 6.3.2 Preventing EEPROM Corruption 6.4 I/O Memory 6.4.1 General Purpose I/O Registers 6.5 Register Description 6.5.1 EEARH and EEARL – The EEPROM Address Register 6.5.2 EEDR – The EEPROM Data Register 6.5.3 EECR – The EEPROM Control Register 6.5.4 GPIOR2 – General Purpose I/O Register 2 6.5.5 GPIOR1 – General Purpose I/O Register 1 6.5.6 GPIOR0 – General Purpose I/O Register 0 7. System Clock and Clock Options 7.1 Clock Systems and their Distribution 7.1.1 CPU Clock – clkCPU 7.1.2 I/O Clock – clkI/O 7.1.3 Flash Clock – clkFLASH 7.1.4 Asynchronous Timer Clock – clkASY 7.1.5 ADC Clock – clkADC 7.2 Clock Sources 7.2.1 Default Clock Source 7.2.2 Clock Startup Sequence 7.2.3 Clock Source Connections 7.3 Low Power Crystal Oscillator 7.4 Full Swing Crystal Oscillator 7.5 Low Frequency Crystal Oscillator 7.6 Calibrated Internal RC Oscillator 7.7 128 kHz Internal Oscillator 7.8 External Clock 7.9 Clock Output Buffer 7.10 Timer/Counter Oscillator 7.11 System Clock Prescaler 7.12 Register Description 7.12.1 OSCCAL – Oscillator Calibration Register 7.12.2 CLKPR – Clock Prescale Register 8. Power Management and Sleep Modes 8.1 Overview 8.2 Sleep Modes 8.3 Idle Mode 8.4 ADC Noise Reduction Mode 8.5 Power-down Mode 8.6 Power-save Mode 8.7 Standby Mode 8.8 Extended Standby Mode 8.9 Power Reduction Register 8.10 Minimizing Power Consumption 8.10.1 Analog to Digital Converter 8.10.2 Analog Comparator 8.10.3 Brown-out Detector 8.10.4 Internal Voltage Reference 8.10.5 Watchdog Timer 8.10.6 Port Pins 8.10.7 On-chip Debug System 8.11 Register Description 8.11.1 SMCR – Sleep Mode Control Register 8.11.2 PRR – Power Reduction Register 9. System Control and Reset 9.1 Resetting the AVR 9.2 Reset Sources 9.2.1 Power-on Reset 9.2.2 External Reset 9.2.3 Brown-out Detection 9.2.4 Watchdog Reset 9.3 Internal Voltage Reference 9.3.1 Voltage Reference Enable Signals and Start-up Time 9.4 Watchdog Timer 9.5 Register Description 9.5.1 MCUSR – MCU Status Register 9.5.2 WDTCSR – Watchdog Timer Control Register 10. Interrupts 10.1 Interrupt Vectors in ATmega644 10.1.1 Moving Interrupts Between Application and Boot Space 10.2 Register Description 10.2.1 MCUCR – MCU Control Register 11. External Interrupts 11.1 Register Description 11.1.1 EICRA – External Interrupt Control Register A 11.1.2 EIMSK – External Interrupt Mask Register 11.1.3 EIFR – External Interrupt Flag Register 11.1.4 PCICR – Pin Change Interrupt Control Register 11.1.5 PCIFR – Pin Change Interrupt Flag Register 11.1.6 PCMSK3 – Pin Change Mask Register 3 11.1.7 PCMSK2 – Pin Change Mask Register 2 11.1.8 PCMSK1 – Pin Change Mask Register 1 11.1.9 PCMSK0 – Pin Change Mask Register 0 12. I/O-Ports 12.1 Introduction 12.2 Ports as General Digital I/O 12.2.1 Configuring the Pin 12.2.2 Toggling the Pin 12.2.3 Switching Between Input and Output 12.2.4 Reading the Pin Value 12.2.5 Digital Input Enable and Sleep Modes 12.2.6 Unconnected Pins 12.3 Alternate Port Functions 12.3.1 Alternate Functions of Port A 12.3.2 Alternate Functions of Port B 12.3.3 Alternate Functions of Port C 12.3.4 Alternate Functions of Port D Register Description 12.3.5 MCUCR – MCU Control Register 12.3.6 PORTA – Port A Data Register 12.3.7 DDRA – Port A Data Direction Register 12.3.8 PINA – Port A Input Pins Address 12.3.9 PORTB – Port B Data Register 12.3.10 DDRB – Port B Data Direction Register 12.3.11 PINB – Port B Input Pins Address 12.3.12 PORTC – Port C Data Register 12.3.13 DDRC – Port C Data Direction Register 12.3.14 PINC – Port C Input Pins Address 12.3.15 PORTD – Port D Data Register 12.3.16 DDRD – Port D Data Direction Register 12.3.17 PIND – Port D Input Pins Address 13. 8-bit Timer/Counter0 with PWM 13.1 Feature 13.2 Overview 13.2.1 Registers 13.2.2 Definitions 13.3 Timer/Counter Clock Sources 13.4 Counter Unit 13.5 Output Compare Unit 13.5.1 Force Output Compare 13.5.2 Compare Match Blocking by TCNT0 Write 13.5.3 Using the Output Compare Unit 13.6 Compare Match Output Unit 13.6.1 Compare Output Mode and Waveform Generation 13.7 Modes of Operation 13.7.1 Normal Mode 13.7.2 Clear Timer on Compare Match (CTC) Mode 13.7.3 Fast PWM Mode 13.7.4 Phase Correct PWM Mode 13.8 Timer/Counter Timing Diagrams 13.9 Register Description 13.9.1 TCCR0A – Timer/Counter Control Register A 13.9.2 TCCR0B – Timer/Counter Control Register B 13.9.3 TCNT0 – Timer/Counter Register 13.9.4 OCR0A – Output Compare Register A 13.9.5 OCR0B – Output Compare Register B 13.9.6 TIMSK0 – Timer/Counter Interrupt Mask Register 13.9.7 TIFR0 – Timer/Counter 0 Interrupt Flag Register 14. 16-bit Timer/Counter1 with PWM 14.1 Features 14.2 Overview 14.2.1 Registers 14.2.2 Definitions 14.3 Accessing 16-bit Registers 14.3.1 Reusing the Temporary High Byte Register 14.4 Timer/Counter Clock Sources 14.5 Counter Unit 14.6 Input Capture Unit 14.6.1 Input Capture Trigger Source 14.6.2 Noise Canceler 14.6.3 Using the Input Capture Unit 14.7 Output Compare Units 14.7.1 Force Output Compare 14.7.2 Compare Match Blocking by TCNTn Write 14.7.3 Using the Output Compare Unit 14.8 Compare Match Output Unit 14.8.1 Compare Output Mode and Waveform Generation 14.9 Modes of Operation 14.9.1 Normal Mode 14.9.2 Clear Timer on Compare Match (CTC) Mode 14.9.3 Fast PWM Mode 14.9.4 Phase Correct PWM Mode 14.9.5 Phase and Frequency Correct PWM Mode 14.10 Timer/Counter Timing Diagrams 14.11 Register Description 14.11.1 TCCR1A – Timer/Counter1 Control Register A 14.11.2 TCCR1B – Timer/Counter1 Control Register B 14.11.3 TCCR1C – Timer/Counter1 Control Register C 14.11.4 TCNT1H and TCNT1L –Timer/Counter1 14.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A 14.11.6 OCR1BH and OCR1BL – Output Compare Register 1 B 14.11.7 ICR1H and ICR1L – Input Capture Register 1 14.11.8 TIMSK1 – Timer/Counter1 Interrupt Mask Register 14.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register 15. 8-bit Timer/Counter2 with PWM and Asynchronous Operation 15.1 Features 15.2 Overview 15.2.1 Registers 15.2.2 Definitions 15.3 Timer/Counter Clock Sources 15.4 Counter Unit 15.5 Output Compare Unit 15.5.1 Force Output Compare 15.5.2 Compare Match Blocking by TCNT2 Write 15.5.3 Using the Output Compare Unit 15.6 Compare Match Output Unit 15.6.1 Compare Output Mode and Waveform Generation 15.7 Modes of Operation 15.7.1 Normal Mode 15.7.2 Clear Timer on Compare Match (CTC) Mode 15.7.3 Fast PWM Mode 15.7.4 Phase Correct PWM Mode 15.8 Timer/Counter Timing Diagrams 15.9 Asynchronous Operation of Timer/Counter2 15.10 Timer/Counter Prescaler 15.11 Register Description 15.11.1 TCCR2A – Timer/Counter Control Register A 15.11.2 TCCR2B – Timer/Counter Control Register B– 15.11.3 TCNT2 – Timer/Counter Register 15.11.4 OCR2A – Output Compare Register A 15.11.5 OCR2B – Output Compare Register B 15.11.6 ASSR – Asynchronous Status Register 15.11.7 TIMSK2 – Timer/Counter2 Interrupt Mask Register 15.11.8 TIFR2 – Timer/Counter2 Interrupt Flag Register 15.11.9 GTCCR – General Timer/Counter Control Register 16. SPI – Serial Peripheral Interface 16.1 Features 16.2 Overview 16.3 SS Pin Functionality 16.3.1 Slave Mode 16.3.2 Master Mode 16.4 Data Modes 16.5 Register Description 16.5.1 SPCR – SPI Control Register 16.5.2 SPSR – SPI Status Register 16.5.3 SPDR – SPI Data Register 17. USART 17.1 Features 17.2 Overview 17.3 Clock Generation 17.3.1 Internal Clock Generation – The Baud Rate Generator 17.3.2 Double Speed Operation (U2Xn) 17.3.3 External Clock 17.3.4 Synchronous Clock Operation 17.4 Frame Formats 17.4.1 Parity Bit Calculation 17.5 USART Initialization 17.6 Data Transmission – The USART Transmitter 17.6.1 Sending Frames with 5 to 8 Data Bit 17.6.2 Sending Frames with 9 Data Bit 17.6.3 Transmitter Flags and Interrupts 17.6.4 Parity Generator 17.6.5 Disabling the Transmitter 17.7 Data Reception – The USART Receiver 17.7.1 Receiving Frames with 5 to 8 Data Bits 17.7.2 Receiving Frames with 9 Data Bits 17.7.3 Receive Compete Flag and Interrupt 17.7.4 Receiver Error Flags 17.7.5 Parity Checker 17.7.6 Disabling the Receiver 17.7.7 Flushing the Receive Buffer 17.8 Asynchronous Data Reception 17.8.1 Asynchronous Clock Recovery 17.8.2 Asynchronous Data Recovery 17.8.3 Asynchronous Operational Range 17.9 Multi-processor Communication Mode 17.9.1 Using MPCMn 17.10 Register Description 17.10.1 UDRn – USART I/O Data Register n 17.10.2 UCSRnA – USART Control and Status Register A 17.10.3 UCSRnB – USART Control and Status Register n B 17.10.4 UCSRnC – USART Control and Status Register n C 17.10.5 UBRRnL and UBRRnH – USART Baud Rate Registers 17.11 Examples of Baud Rate Setting 18. USART in SPI Mode 18.1 Features 18.2 Overview 18.3 Clock Generation 18.4 SPI Data Modes and Timing 18.5 Frame Formats 18.5.1 USART MSPIM Initialization 18.6 Data Transfer 18.6.1 Transmitter and Receiver Flags and Interrupts 18.6.2 Disabling the Transmitter or Receiver 18.7 Register Description 18.7.1 UDRn – USART MSPIM I/O Data Register 18.7.2 UCSRnA – USART MSPIM Control and Status Register n A 18.7.3 UCSRnB – USART MSPIM Control and Status Register n B 18.7.4 UCSRnC – USART MSPIM Control and Status Register n C 18.7.5 UBRRnL and UBRRnH –USART MSPIM Baud Rate Registers 18.8 AVR USART MSPIM vs. AVR SPI 19. 2-wire Serial Interface 19.1 Features 19.2 2-wire Serial Interface Bus Definition 19.2.1 TWI Terminology 19.2.2 Electrical Interconnection 19.3 Data Transfer and Frame Format 19.3.1 Transferring Bits 19.3.2 START and STOP Conditions 19.3.3 Address Packet Format 19.3.4 Data Packet Format 19.3.5 Combining Address and Data Packets into a Transmission 19.4 Multi-master Bus Systems, Arbitration and Synchronization 19.5 Overview of the TWI Module 19.5.1 SCL and SDA Pins 19.5.2 Bit Rate Generator Unit 19.5.3 Bus Interface Unit 19.5.4 Address Match Unit 19.5.5 Control Unit 19.6 Using the TWI 19.7 Transmission Modes 19.7.1 Master Transmitter Mode 19.7.2 Master Receiver Mode 19.7.3 Slave Receiver Mode 19.7.4 Slave Transmitter Mode 19.7.5 Miscellaneous States 19.7.6 Combining Several TWI Modes 19.8 Multi-master Systems and Arbitration 19.9 Register Description 19.9.1 TWBR – TWI Bit Rate Register 19.9.2 TWCR – TWI Control Register 19.9.3 TWSR – TWI Status Register 19.9.4 TWDR – TWI Data Register 19.9.5 TWAR – TWI (Slave) Address Register 19.9.6 TWAMR – TWI (Slave) Address Mask Register 20. Analog Comparator 20.1 Overview 20.2 Analog Comparator Multiplexed Input 20.3 Register Description 20.3.1 ADCSRB – ADC Control and Status Register B 20.3.2 ACSR – Analog Comparator Control and Status Register 20.3.3 DIDR1 – Digital Input Disable Register 1 21. Analog-to-digital Converter 21.1 Features 21.2 Overview 21.3 Operation 21.4 Starting a Conversion 21.5 Prescaling and Conversion Timing 21.5.1 Differential Gain Channels 21.6 Changing Channel or Reference Selection 21.6.1 ADC Input Channels 21.6.2 ADC Voltage Reference 21.7 ADC Noise Canceler 21.7.1 Analog Input Circuitry 21.7.2 Analog Noise Canceling Techniques 21.7.3 Offset Compensation Schemes 21.7.4 ADC Accuracy Definitions 21.8 ADC Conversion Result 21.9 Register Description 21.9.1 ADMUX – ADC Multiplexer Selection Register 21.9.2 ADCSRA – ADC Control and Status Register A 21.9.3 ADCL and ADCH – The ADC Data Register ADLAR = 0 ADLAR = 1 21.9.4 ADCSRB – ADC Control and Status Register B 21.9.5 DIDR0 – Digital Input Disable Register 0 22. JTAG Interface and On-chip Debug System 22.0.1 Features 22.1 Overview 22.2 TAP – Test Access Port 22.3 TAP Controller 22.4 Using the Boundary-scan Chain 22.5 Using the On-chip Debug System 22.6 On-chip Debug Specific JTAG Instructions 22.6.1 PRIVATE0; 0x8 22.6.2 PRIVATE1; 0x9 22.6.3 PRIVATE2; 0xA 22.6.4 PRIVATE3; 0xB 22.7 Using the JTAG Programming Capabilities 22.8 Bibliography 22.9 Register Description 22.9.1 OCDR – On-chip Debug Register 23. IEEE 1149.1 (JTAG) Boundary-scan 23.1 Features 23.2 Overview 23.3 Data Registers 23.3.1 Bypass Register 23.3.2 Device Identification Register Version Part Number Manufacturer ID 23.3.3 Reset Register 23.3.4 Boundary-scan Chain 23.4 Boundary-scan Specific JTAG Instructions 23.4.1 EXTEST; 0x0 23.4.2 IDCODE; 0x1 23.4.3 SAMPLE_PRELOAD; 0x2 23.4.4 AVR_RESET; 0xC 23.4.5 BYPASS; 0xF 23.5 Boundary-scan Chain 23.5.1 Scanning the Digital Port Pins 23.5.2 Scanning the RESET Pin 23.6 ATmega644 Boundary-scan Order 23.7 Boundary-scan Description Language Files 23.8 Register Description 23.8.1 MCUCR – MCU Control Register 23.8.2 MCUSR – MCU Status Register 24. Boot Loader Support – Read-While-Write Self-Programming 24.1 Features 24.2 Overview 24.3 Application and Boot Loader Flash Sections 24.3.1 Application Section 24.3.2 BLS – Boot Loader Section 24.4 Read-While-Write and No Read-While-Write Flash Sections 24.4.1 RWW – Read-While-Write Section 24.4.2 NRWW – No Read-While-Write Section 24.5 Boot Loader Lock Bits 24.6 Entering the Boot Loader Program 24.7 Addressing the Flash During Self-Programming 24.8 Self-Programming the Flash 24.8.1 Performing Page Erase by SPM 24.8.2 Filling the Temporary Buffer (Page Loading) 24.8.3 Performing a Page Write 24.8.4 Using the SPM Interrupt 24.8.5 Consideration While Updating BLS 24.8.6 Prevent Reading the RWW Section During Self-Programming 24.8.7 Setting the Boot Loader Lock Bits by SPM 24.8.8 EEPROM Write Prevents Writing to SPMCSR 24.8.9 Reading the Fuse and Lock Bits from Software 24.8.10 Reading the Signature Row from Software 24.8.11 Preventing Flash Corruption 24.8.12 Programming Time for Flash when Using SPM 24.8.13 Simple Assembly Code Example for a Boot Loader 24.8.14 ATmega644 Boot Loader Parameters 24.9 Register Description 24.9.1 SPMCSR – Store Program Memory Control and Status Register 25. Memory Programming 25.1 Program And Data Memory Lock Bits 25.2 Fuse Bits 25.2.1 Latching of Fuses 25.3 Signature Bytes 25.4 Calibration Byte 25.5 Page Size 25.6 Parallel Programming Parameters, Pin Mapping, and Commands 25.6.1 Signal Names 25.7 Parallel Programming 25.7.1 Enter Programming Mode 25.7.2 Considerations for Efficient Programming 25.7.3 Chip Erase 25.7.4 Programming the Flash 25.7.5 Programming the EEPROM 25.7.6 Reading the Flash 25.7.7 Reading the EEPROM 25.7.8 Programming the Fuse Low Bits 25.7.9 Programming the Fuse High Bits 25.7.10 Programming the Extended Fuse Bits 25.7.11 Programming the Lock Bits 25.7.12 Reading the Fuse and Lock Bits 25.7.13 Reading the Signature Bytes 25.7.14 Reading the Calibration Byte 25.7.15 Parallel Programming Characteristics 25.8 Serial Downloading 25.8.1 Serial Programming Pin Mapping 25.8.2 Serial Programming Algorithm 25.9 Serial Programming Instruction set 25.9.1 Serial Programming Characteristics 25.10 Programming via the JTAG Interface 25.10.1 Programming Specific JTAG Instructions 25.10.2 AVR_RESET (0xC) 25.10.3 PROG_ENABLE (0x4) 25.10.4 PROG_COMMANDS (0x5) 25.10.5 PROG_PAGELOAD (0x6) 25.10.6 PROG_PAGEREAD (0x7) 25.10.7 Data Registers 25.10.8 Reset Register 25.10.9 Programming Enable Register 25.10.10 Programming Command Register 25.10.11 Flash Data Byte Register 25.10.12 Programming Algorithm 25.10.13 Entering Programming Mode 25.10.14 Leaving Programming Mode 25.10.15 Performing Chip Erase 25.10.16 Programming the Flash 25.10.17 Reading the Flash 25.10.18 Programming the EEPROM 25.10.19 Reading the EEPROM 25.10.20 Programming the Fuses 25.10.21 Programming the Lock Bits 25.10.22 Reading the Fuses and Lock Bits 25.10.23 Reading the Signature Bytes 25.10.24 Reading the Calibration Byte 26. Electrical Characteristics 26.1 Absolute Maximum Ratings* 26.2 DC Characteristics 26.3 Speed Grades 26.4 Clock Characteristics 26.4.1 External Clock Drive Waveforms 26.4.2 External Clock Drive 26.5 System and Reset Characteristics 26.6 2-wire Serial Interface Characteristics 26.7 SPI Timing Characteristics 26.8 ADC Characteristics 27. Typical Characteristics 27.1 Active Supply Current 27.2 Idle Supply Current 27.3 Supply Current of IO modules Example 27.4 Power-down Supply Current 27.5 Power-save Supply Current 27.6 Standby Supply Current 27.7 Pin Pull-up 27.8 Pin Driver Strength 27.9 Pin Threshold and Hysteresis 27.10 BOD Threshold and Analog Comparator Offset 27.11 Internal Oscillator Speed 27.12 Current Consumption of Peripheral Units 28. Register Summary 29. Instruction Set Summary 30. Ordering Information 30.1 ATmega644 31. Packaging Information 31.1 44A 31.2 40P6 31.3 44M1 32. Errata 32.1 Rev. C 32.2 Rev. B 32.3 Rev. A 33. Datasheet Revision History 33.1 Rev. 2593O - 02/12 33.2 Rev. 2593N - 07/10 33.3 Rev. 2593M - 08/07 33.4 Rev. 2593L - 02/07 33.5 Rev. 2593K - 01/07 33.6 Rev. 2593J - 09/06 33.7 Rev. 2593I - 08/06 33.8 Rev. 2593H - 07/06 33.9 Rev. 2593G - 06/06 33.10 Rev. 2593F - 04/06 33.11 Rev. 2593E - 04/06 33.12 Rev. 2593D - 04/06 33.13 Rev. 2593C - 03/06 33.14 Rev. 2593B - 03/06 33.15 Rev. 2593A-06/05 Table of Contents