Datasheet LT3781 (Analog Devices) - 8

LT3781
U U U PI FU CTIO S
The error amplifier is typically configured using a feedback
BG (Pin 15):
Bottom Side Primary Switch/Forward Switch RC network to realize an integrator circuit. This circuit Output Driver. This pin can be connected directly to creates the dominant pole for the converter regulation gate(s) of primary bottom side and forward switches if feedback loop. Integrator characteristics are dominated small FETs are used (CGATE total < 5000pF), however, the by the value of the capacitor connected from the VC pin to use of a gate drive buffer is recommended for peak the VFB pin and the feedback resistor connected to the VFB efficiencies. pin. Specific integrator characteristics can be configured The BG output is enabled at the start of each oscillator to optimize transient response. cycle in phase with the TG pin but is timed to “lag” the TG The error amplifier can also be configured as a output during turn-on and “lead” the TG output during transimpedance amplifier for use in secondary-side con- turn-off. These delays force the concentration of transi- troller applications. (See the Applications Information tional losses onto the bottom side primary switch. section for configuration and compensation details) An adaptive blanking circuit disables the current sense
SENSE (Pin 11):
Current Sense Amplifier (CSA) function (via the SENSE pin) while the BG pin is below 5V. Noninverting Input. Current is monitored via a ground
BSTREF (Pin 18):
V referenced current sense resistor, typically in series with BST Supply Reference. Typically con- nects to source of topside external power FET switch. the source of the bottom side switch FET. Internal current limit circuitry provides for a maximum peak value of
TG (Pin 19):
Topside (Boosted) Primary Output Driver. 150mV across the sense resistor during normal opera- This pin can be connected directly to gate of primary tion. topside switch if small FETs are used (CGATE < 5000pF), however, the use of a gate drive buffer is recommended for
SG (Pin 12):
Synchronous Switch Output Driver. This pin peak efficiencies. can be connected directly to gate of synchronous switch if small FETs are used (C
V
GATE < 5000pF), however, the use
BST (Pin 20):
Topside Primary Driver Bootstrapped Sup- of a gate drive buffer is recommended for peak efficien- ply. This “boosted” supply rail is referenced to the BSTREF cies. pin. The SG pin output is synchronized and out-of-phase with Supply voltage is maintained by a bootstrap capacitor tied the BG output. The control timing of the SG output cause from the VBST pin to the boosted supply reference (BSTREF) it to “lead” the primary switch path during turn-on by pin. The charge on the capacitor is refreshed each switch 150nS. cycle through a Schottky diode connected from the VCC supply (cathode) to the V
V
BST pin (anode). The bootstrap
CC (Pin 13):
IC Local Power Supply Input. Bypass with at capacitor (C a capacitor at least 10 times greater than C5V BOOST) must be at least 100 times greater than REF. LT3781 the total load capacitance on the TG pin. A capacitor in the incorporates undervoltage lockout that disables switching range of 0.1µF to 1.0µF is generally adequate for most functions if VCC is below 8.4V. The LT3781 supports applications. The bootstrap diode must have a reverse operational VCC power supply voltages from 9V to 18V breakdown voltage greater than the converter V (20V absolute maximum). An 18V clamp on the V IN. The CC pin is LT3781 supports operational V enabled during shutdown mode, preventing a trickle start BST supply voltages up to 90V (absolute maximum) referenced to ground. circuit from pulling that pin above maximum operational Undervoltage Lockout disables the topside switch until levels during IC shutdown. VBST – BSTREF > 7.0V for start-up protection of the
PWRGND (Pin 14):
Output Driver Ground Reference. topside switch. Connect through low impedance trace to VIN decoupling capacitor. 3781f 8