Datasheet AD420 (Analog Devices) - 10

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AD420 Data Sheet APPLICATIONS INFORMATION CURRENT OUTPUT Table 7. Buffer Amplifier Configuration
The AD420 can provide 4 mA–20 mA, 0 mA–20 mA, or 0 mA–
R1 R2 R3 VOUT
24 mA output without any active external components. Filter Open Open 0 0 V − 5 V capacitors C1 and C2 can be any type of low cost ceramic Open R R capacitors. To meet the specified ful -scale settling time of 3 ms, R Open R ±5 V low dielectric absorption capacitors (NPO) are required. R 2R 2R ±10 V Suitable values are C1 = 0.01 µF and C2 = 0.01 µF. Suitable R = 5 kΩ.
VCC 0.1µF V 0.1µF OPTIONAL SPAN AND ZERO TRIM LL C1 C2
For users who would like lower than the specified values of
2 20 21 23
offset and gain error, Figure 8 shows a simple way to trim these
RANGE 5 SELECT 1
parameters. Care should be taken to select low drift resistors
RANGE 4 SELECT 2
because they affect the temperature drift performance of
IOUT (4mA TO 20mA) CLEAR 6 18
the DAC.
AD420 R LATCH 7 LOAD
The adjustment algorithm is iterative. The procedure for
8 CLOCK
trimming the AD420 in the 4 mA–20 mA mode can be
9 DATA IN
accomplished as follows:
14 15 11
006
REF OUT REF IN GND
1. Offset adjust. Load all zeros. Adjust RZERO for 00494- Figure 6. Standard Configuration 4.00000 mA of output current. 2. Gain adjust. Load al ones. Adjust RSPAN for 19.99976 mA
DRIVING INDUCTIVE LOADS
(FS − 1 LSB) of output current. When driving inductive or poorly defined loads ,connect a 0.01 µF capacitor between I Return to Step I and iterate until convergence is obtained. OUT (Pin 18) and GND (Pin 11). This ensures stability of the AD420 with loads beyond 50 mH. There is no
VCC V
maximum capacitance limit. The capacitive component of the
LL 0.1µF C1 C2 0.1µF
load may cause slower settling, though this may be masked by
5kΩ 2 20 21 23
the settling time of the AD420. A programmed change in the
RSPAN2 RANGE 5 SELECT 1
current may cause a back EMF voltage on the output that may
19 RANGE BOOST 4
exceed the compliance of the AD420. To prevent this voltage
SELECT 2 CLEAR 6 I
from exceeding the supply rails connect protective diodes
OUT (4mA TO 20mA) AD420 18
between I
LATCH 7 R
OUT and each of VCC and GND.
LOAD 8 CLOCK VOLTAGE-MODE OUTPUT 9 DATA IN
Since the AD420 is a single supply device, it is necessary to add
14 15 16 11 REF OUT
an external buffer amplifier to the VOUT pin to obtain a selection
500Ω
of bipolar output voltage ranges as shown in Figure 7.
RSPAN
008
10kΩ GND VCC RZERO
00494-
0.1µF VLL
Figure 8. Offset and Gain Adjust
0.1µF C1 C2
Variation of RZERO between REF OUT (5 V) and GND leads
2 20 21 23 RANGE 5
to an offset adjust range from −1.5 mA to 6 mA, (1.5 mA/V
SELECT 1 RANGE
centered at 1 V).
4 SELECT 2 VOUT CLEAR 6 17
The 5 kΩ RSPAN2 resistor is connected in paral el with the
AD420 VOUT LATCH 7
internal 40 W sense resistor, which leads to a gain increase of
R3 8
+0.8%.
CLOCK R1 R2 9 DATA IN
As RSPAN is changed to 500 Ω, the voltage on REF IN is
14 15 11 REF OUT REF IN GND
007 attenuated by the combination of RSPAN and the 30 kΩ REF IN 00494- input resistance. When added together with RSPAN2 this Figure 7. results in an adjustment range of −0.8% to +0.8%. Rev. I | Page 10 of 16 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TIMING REQUIREMENTS THREE-WIRE INTERFACE THREE-WIRE INTERFACE FAST EDGES ON DIGITAL INPUT ASYNCHRONOUS INTERFACE TERMINOLOGY THEORY OF OPERATION APPLICATIONS INFORMATION CURRENT OUTPUT DRIVING INDUCTIVE LOADS VOLTAGE-MODE OUTPUT OPTIONAL SPAN AND ZERO TRIM THREE-WIRE INTERFACE USING MULTIPLE DACS WITH FAULT DETECT ASYNCHRONOUS INTERFACE USING OPTOCOUPLERS MICROPROCESSOR INTERFACE AD420-TO-MC68HC11 (SPI BUS) INTERFACE AD420 TO MICROWIRE INTERFACE EXTERNAL BOOST FUNCTION AD420 PROTECTION TRANSIENT VOLTAGE PROTECTION BOARD LAYOUT AND GROUNDING POWER SUPPLIES AND DECOUPLING OUTLINE DIMENSIONS ORDERING GUIDE