AD420Data SheetTERMINOLOGY ResolutionGain Error For 16-bit resolution, 1 LSB = 0.0015% of the FSR. In the Gain error is a measure of the output error between an ideal 4 mA–20 mA range 1 LSB = 244 nA. DAC and the actual device output with al 1s loaded after offset error has been adjusted out. Integral Nonlinearity Analog Devices defines integral nonlinearity as the maximum Offset Error deviation of the actual, adjusted DAC output from the ideal Offset error is the deviation of the output current from its ideal analog output (a straight line drawn from 0 to FS – 1 LSB) for value expressed as a percentage of the ful scale output with al any bit combination. This is also referred to as relative accuracy. 0s loaded in the DAC. Differential NonlinearityDrift Differential nonlinearity is the measure of the change in the Drift is the change in a parameter (such as gain and offset) over analog output, normalized to full scale, associated with an LSB a specified temperature range. The drift temperature coefficient, change in the digital input code. Monotonic behavior requires specified in ppm/°C, is calculated by measuring the parameter that the differential linearity error be greater than –1 LSB over at TMIN, 25°C, and TMAX and dividing the change in the the temperature range of interest. parameter by the corresponding temperature change. MonotonicityCurrent Loop Voltage Compliance A DAC is monotonic if the output either increases or remains The voltage compliance is the maximum voltage at the IOUT pin for constant for increasing digital inputs with the result that the which the output current wil be equal to the programmed value. output will always be a single-valued function of the input. Rev. I | Page 8 of 16 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TIMING REQUIREMENTS THREE-WIRE INTERFACE THREE-WIRE INTERFACE FAST EDGES ON DIGITAL INPUT ASYNCHRONOUS INTERFACE TERMINOLOGY THEORY OF OPERATION APPLICATIONS INFORMATION CURRENT OUTPUT DRIVING INDUCTIVE LOADS VOLTAGE-MODE OUTPUT OPTIONAL SPAN AND ZERO TRIM THREE-WIRE INTERFACE USING MULTIPLE DACS WITH FAULT DETECT ASYNCHRONOUS INTERFACE USING OPTOCOUPLERS MICROPROCESSOR INTERFACE AD420-TO-MC68HC11 (SPI BUS) INTERFACE AD420 TO MICROWIRE INTERFACE EXTERNAL BOOST FUNCTION AD420 PROTECTION TRANSIENT VOLTAGE PROTECTION BOARD LAYOUT AND GROUNDING POWER SUPPLIES AND DECOUPLING OUTLINE DIMENSIONS ORDERING GUIDE