Datasheet ADXRS453 (Analog Devices) - 8

Data Sheet ADXRS453 TYPICAL PERFORMANCE CHARACTERISTICS 20 40 18 35 ) 16 ) % % ( ( 30 N 14 N IO IO T T A A 25 L 12 L PU PU 10 20 PO PO F F O 8 O T T 15 N N E 6 E C C 10 PER 4 PER 2 5 0 0
9 06
–2.0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6 2.0
0 -00 5-
–2.0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6 2.0
55
ERROR (°/sec)
1 915 0
ERROR (°/sec)
09 Figure 5. SOIC_CAV Null Accuracy at 25°C Figure 8. LCC_V Null Accuracy at 25°C
30 30 25 25 (%) (%) N N IO 20 IO T 20 T A A L L PU PU 15 15 PO PO F F O O T T N 10 N E 10 E C C R R PE PE 5 5 0 0 .0 5 0 5 0 5 0 5 0 5 0 5 0 .0 .5 0 5 0 5 0 5 0
07
0 .5 .0 .5
10 0
0. 1. 1. 2. 2. 3. 0. 1. 1. 2. 2. 3.
0
–3
5-
–2. –2. –1. –1. –0. –3. –2 –2 –1 –1 –0
5- 15 15
ERROR (°/sec)
09
ERROR (°/sec)
09 Figure 6. SOIC_CAV Null Drift over Temperature Figure 9. LCC_V Null Drift over Temperature
25 25 ) 20 % 20 (%) N ( N IO IO T AT 15 A 15 L UL P PU O P PO F F O 10 10 O T NT N E C RCE E ER P 5 P 5 0 0 0 5 0 5 0 5 0 5 0 5 0 5 0 0 5 0 5 0 5 0
08
–3. –2. –2. –1. –1. –0. 0. 1. 1. 2. 2. 3.
0
00 01 01 02 02 03
5-
.030 .025 .020 .015 .010 .005 0. 0. 0. 0. 0. 0.
11 0
CHANGE IN SENSITIVITY (%)
15
–0 –0 –0 –0 –0 –0
5- 09 15
CHANGE IN SENSITIVITY (%)
09 Figure 7. SOIC_CAV Sensitivity Error at 25°C Figure 10. LCC_V Sensitivity Error at 25°C Rev. B | Page 7 of 32 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Rate Sensitive Axis ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Continuous Self-Test Mechanical Performance Noise Performance Applications Information Calibrated Performance Mechanical Considerations for Mounting Application Circuits ADXRS453 Signal Chain Timing SPI Communication Protocol Command/Response Device Data Latching SPI Timing Characteristics Command/Response Bit Definitions SQ2 to SQ0 Bits SM2 to SM0 Bits A8 to A0 Bits D15 to D0 Bits P Bit SPI Bit RE Bit DU Bit ST1 and ST0 Bits P0 Bit P1 Bit Fault Register Bit Definitions Fail Bit AMP Bit OV Bit UV Bit PLL Bit Q Bit NVM Bit POR Bit PWR Bit CST Bit CHK Bit Recommended Start-Up Sequence with CHK Bit Assertion Rate Data Format Memory Map and Registers Memory Map Memory Register Definitions Rate (RATEx) Registers Temperature (TEMx) Registers Low CST (LOCSTx) Registers High CST (HICSTx) Registers Quad Memory (QUADx) Registers Fault (FAULTx) Registers Part ID (PIDx) Registers Serial Number (SNx) Registers Package Orientation and Layout Information Solder Profile Package Marking Codes Outline Dimensions Ordering Guide