Datasheet ADIS16240 (Analog Devices) - 5

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ADIS16240 Data Sheet TIMING SPECIFICATIONS
TA = 25°C, VDD = 3.3 V, unless otherwise noted.
Table 2. Parameter Description Min1 Ty p Max
1
Unit
fSCLK Serial clock rate2 0.01 2.5 MHz tDATARATE Chip select period2 60 μs tCS Chip select to clock edge 120 ns tDAV Data output valid after SCLK edge 30 ns tDSU Data input setup time before SCLK rising edge 20 ns tDHD Data input hold time after SCLK rising edge 20 ns tDF Data output fall time 10 25 ns tDR Data output rise time 10 25 ns tSFS CS high after SCLK edge 430 ns 1 Guaranteed by design; typical specifications are not tested or guaranteed. 2 Based on sample rate selection.
Timing Diagrams tDATARATE CS
2 00 3-
SCLK
13 08 Figure 2. SPI Chip Select Timing
CS tCS tSFS 1 2 3 4 5 6 15 16 SCLK tDAV DOUT MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB t t DSU DHD DIN W/R A6 A5 A4 A3 A2 D2 D1 LSB
03 0 3- 13 08 Figure 3. SPI Timing (Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1) Rev. C | Page 4 of 20 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Sensing Element Data Sampling and Processing User Interface SPI Interface User Registers Capture Basic Operation SPI Write Commands Memory Map Output Data Registers Processing Sensor Data Event Recorder Internal Trigger Setup External Trigger Setup Buffer Memory Configuration Event Organization Reading Event Data Transient Behavior During Capture Operational Control Internal Sample Rate Global Commands Input/Output Lines Offset Adjustment Diagnostics Clock Checksum Flash Memory Endurance Management Applications Information Assembly Interface Printed Circuit Board (PCB) Outline Dimensions Ordering Guide