Datasheet ADXL312 (Analog Devices) - 7

ADXL312 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS K L I/O /SC D L D NC V NC NC NC NC SC NC 32 31 30 29 28 27 26 25 GND 1 24 SDA/SDI/SDIO RESERVED 2 23 SPO/ALT ADDRESS GND 3 22 RESERVED ADXL312 GND 4 21 INT2 TOP VIEW V 5 20 INT1 S (Not to Scale) CS 6 19 NC RESERVED 7 18 NC NC 8 17 NC 9 10 11 12 13 14 15 16 NC NC NC NC NC NC NC NC NOTES
02 0
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
91-
2. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE.
087 Figure 2. Pin Configuration (Top View)
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 GND This pin must be connected to ground. 2 Reserved Reserved. This pin must be connected to VS or left open. 3 GND This pin must be connected to ground. 4 GND This pin must be connected to ground. 5 VS Supply Voltage. 6 CS Chip Select. 7 Reserved Reserved. This pin must be left open. 8 to19 NC No Connect. Do not connect to this pin. 20 INT1 Interrupt 1 Output. 21 INT2 Interrupt 2 Output. 22 Reserved Reserved. This pin must be connected to GND. 23 SDO/ALT ADDRESS Serial Data Out, Alternate I2C Address Select. 24 SDA/SDI/SDIO Serial Data (I2C), Serial Data In (SPI 4-Wire), Serial Data In/Out (SPI 3-Wire). 25 NC No Connect. Do not connect to this pin. 26 SCL/SCLK Serial Communications Clock. 27 to 30 NC No Connect. Do not connect to this pin. 31 VDD I/O Digital Interface Supply Voltage. 32 NC No Connect. EP The exposed pad must be soldered to the ground plane. Rev. B | Page 6 of 32 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Power Sequencing Power Savings Power Modes Autosleep Mode Standby Mode Serial Communications Serial Port I/O Default states SPI Preventing Bus Traffic Errors I2C Interrupts DATA_READY Activity Inactivity Watermark Overrun FIFO Bypass Mode FIFO Mode Stream Mode Trigger Mode Retrieving Data from FIFO Self-Test Register Map Register Definitions Register 0x00—DEVID (Read Only) Register 0x1E, Register 0x1F, Register 0x20—OFSX, OFSY, OFSZ (Read/Write) Register 0x24—THRESH_ACT (Read/Write) Register 0x25—THRESH_INACT (Read/Write) Register 0x26—TIME_INACT (Read/Write) Register 0x27—ACT_INACT_CTL (Read/Write) ACT AC/DC and INACT AC/DC Bits ACT_x Enable Bits and INACT_x Enable Bits Register 0x2C—BW_RATE (Read/Write) LOW_POWER Bit Rate Bits Register 0x2D—POWER_CTL (Read/Write) Link Bit AUTO_SLEEP Bit Measure Bit Sleep Bit Wake-Up Bits Register 0x2E—INT_ENABLE (Read/Write) Register 0x2F—INT_MAP (Read/Write) Register 0x30—INT_SOURCE (Read Only) Register 0x31—DATA_FORMAT (Read/Write) SELF_TEST Bit SPI Bit INT_INVERT Bit FULL_RES Bit Justify Bit Range Bits Register 0x32 to Register 0x37—DATAX0, DATAX1, DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only) Register 0x38—FIFO_CTL (Read/Write) FIFO_MODE Bits Trigger Bit Samples Bits 0x39—FIFO_STATUS (Read Only) FIFO_TRIG Bit Entries Bits Applications Information Power Supply Decoupling Mechanical Considerations for Mounting Threshold Link Mode Sleep Mode vs. Low Power Mode Using Self-Test Data Formatting of Upper Data Rates Noise Performance Axes of Acceleration Sensitivity Solder Profile Outline Dimensions Ordering Guide Automotive Products