Datasheet ADXL350 (Analog Devices) - 4

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Data Sheet ADXL350 SPECIFICATIONS
TA = 25°C, VS = 2.5 V, VDD I/O = 2.5 V, acceleration = 0 g, and CIO = 0.1 μF, unless otherwise noted. Al minimum and maximum specifications are guaranteed. Typical specifications are not guaranteed.
Table 1. Parameter Test Conditions Min Typ Max Unit
SENSOR INPUT Each axis Measurement Range User selectable ±1, ±2, ±4, ±8 g Nonlinearity Percentage of full scale ±0.5 % Inter-Axis Alignment Error ±0.1 Degrees Cross-Axis Sensitivity1 ±3 % OUTPUT RESOLUTION Each axis All g Ranges 10-bit resolution 10 Bits ±1 g Range Full resolution 10 Bits ±2 g Range Full resolution 11 Bits ±4 g Range Full resolution 12 Bits ±8 g Range Full resolution 13 Bits SENSITIVITY Each axis Sensitivity at XOUT, YOUT, ZOUT Any g-range, full resolution 473.6 512 550.4 LSB/g Scale Factor at XOUT, YOUT, ZOUT Any g-range, full resolution 1.80 1.95 2.10 mg/LSB Sensitivity at XOUT, YOUT, ZOUT ±1 g, 10-bit resolution 473.6 512 550.4 LSB/g Scale Factor at XOUT, YOUT, ZOUT ±1 g, 10-bit resolution 1.80 1.95 2.10 mg/LSB Sensitivity at XOUT, YOUT, ZOUT ±2 g, 10-bit resolution 236.8 256 275.2 LSB/g Scale Factor at XOUT, YOUT, ZOUT ±2 g, 10-bit resolution 3.61 3.91 4.21 mg/LSB Sensitivity at XOUT, YOUT, ZOUT ±4 g, 10-bit resolution 118.4 128 137.6 LSB/g Scale Factor at XOUT, YOUT, ZOUT ±4 g, 10-bit resolution 7.22 7.81 8.40 mg/LSB Sensitivity at XOUT, YOUT, ZOUT ±8 g, 10-bit resolution 59.2 64 68.8 LSB/g Scale Factor at XOUT, YOUT, ZOUT ±8 g, 10-bit resolution 14.45 15.63 16.80 mg/LSB Sensitivity Change Due to Temperature ±0.01 %/°C 0 g BIAS LEVEL Each axis 0 g Output for XOUT, YOUT −150 ±50 +150 Mg 0 g Output for ZOUT −250 ±75 +250 Mg 0 g Offset vs. Temperature (X Axis and Y Axis)2 −0.31 ±0.17 +0.31 mg/°C 0 g Offset vs. Temperature (Z Axis)2 −0.49 ±0.24 +0.49 mg/°C NOISE PERFORMANCE Noise (X-Axis and Y-Axis) 100 Hz data rate, full resolution 1.1 LSB rms Noise (Z-Axis) 100 Hz data rate, full resolution 1.7 LSB rms OUTPUT DATA RATE AND BANDWIDTH User selectable Measurement Rate3 6.25 3200 Hz SELF-TEST4 Data rate ≥ 100 Hz, 2.0 V ≤ VS ≤ 3.6 V Output Change in X-Axis 0.2 2.1 g Output Change in Y-Axis −2.1 −0.2 g Output Change in Z-Axis 0.3 3.4 g POWER SUPPLY Operating Voltage Range (VS) 2.0 2.5 3.6 V Interface Voltage Range (VDD I/O) 1.7 1.8 VS V Supply Current Data rate > 100 Hz 166 µA Data rate < 10 Hz 45 µA Standby Mode Leakage Current 0.1 2 µA Turn-On Time5 Data rate = 3200 Hz 1.4 ms OPERATING TEMPERATURE RANGE −40 +85 oC 1 Cross-axis sensitivity is defined as coupling between any two axes. 2 Offset vs. temperature minimum/maximum specifications are guaranteed by characterization and represent a mean ±3σ distribution. 3 Bandwidth is half the output data rate. 4 Self-test change is defined as the output (g) when the SELF_TEST bit = 1 (in the DATA_FORMAT register) minus the output (g) when the SELF_TEST bit = 0 (in the DATA_FORMAT register). Due to device filtering, the output reaches its final value after 4 × τ when enabling or disabling self-test, where τ = 1/(data rate). 5 Turn-on and wake-up times are determined by the user-defined bandwidth. At a 100 Hz data rate, the turn-on and wake-up times are each approximately 11.1 ms. For other data rates, the turn-on and wake-up times are each approximately τ + 1.1 in milliseconds, where τ = 1/(data rate). Rev. 0 | Page 3 of 36 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Package Information ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Power Sequencing Power Savings Power Modes Auto Sleep Mode Standby Mode Serial Communications SPI Preventing Bus Traffic Errors I2C Interrupts DATA_READY SINGLE_TAP DOUBLE_TAP Activity Inactivity FREE_FALL Watermark Overrun FIFO Bypass Mode FIFO Mode Stream Mode Trigger Mode Retrieving Data from FIFO Self-Test Register Map Register Definitions Register 0x00—DEVID (Read Only) Register 0x1D—THRESH_TAP (Read/Write) Register 0x1E, Register 0x1F, Register 0x20—OFSX, OFSY, OFSZ (Read/Write) Register 0x21—DUR (Read/Write) Register 0x22—Latent (Read/Write) Register 0x23—Window (Read/Write) Register 0x24—THRESH_ACT (Read/Write) Register 0x25—THRESH_INACT (Read/Write) Register 0x26—TIME_INACT (Read/Write) Register 0x27—ACT_INACT_CTL (Read/Write) ACT AC/DC and INACT AC/DC Bits ACT_x Enable Bits and INACT_x Enable Bits Register 0x28—THRESH_FF (Read/Write) Register 0x29—TIME_FF (Read/Write) Register 0x2A—TAP_AXES (Read/Write) Suppress Bit TAP_x Enable Bits Register 0x2B—ACT_TAP_STATUS (Read Only) ACT_x Source and TAP_x Source Bits Asleep Bit Register 0x2C—BW_RATE (Read/Write) LOW_POWER Bit Rate Bits Register 0x2D—POWER_CTL (Read/Write) Link Bit AUTO_SLEEP Bit Measure Bit Sleep Bit Wakeup Bits Register 0x2E—INT_ENABLE (Read/Write) Register 0x2F—INT_MAP (Read/Write) Register 0x30—INT_SOURCE (Read Only) Register 0x31—DATA_FORMAT (Read/Write) SELF_TEST Bit SPI Bit INT_INVERT Bit FULL_RES Bit Justify Bit Range Bits Register 0x32 to Register 0x37—DATAX0, DATAX1, DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only) Register 0x38—FIFO_CTL (Read/Write) FIFO_MODE Bits Trigger Bit Samples Bits 0x39—FIFO_STATUS (Read Only) FIFO_TRIG Bit Entries Bits Applications Information Power Supply Decoupling Mechanical Considerations for Mounting Tap Detection Threshold Link Mode Sleep Mode vs. Low Power Mode Offset Calibration Using Self-Test Axes of Acceleration Sensitivity Layout and Design Recommendations Outline Dimensions Ordering Guide