Datasheet ADXL350 (Analog Devices) - 5

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ADXL350 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 2. PACKAGE INFORMATION Parameter Rating
The information in Figure 2 and Table 4 provide details about Acceleration the package branding for the ADXL350. For a complete listing Any Axis, Unpowered 10,000 g of product availability, see the Ordering Guide section. Any Axis, Powered 10,000 g V −0.3 V to +3.6 V S V −0.3 V to +3.6 V DD I/O
XL350B
Digital Pins −0.3 V to V + 0.3 V or DD I/O 3.6 V, whichever is less
ywVVVV
All Other Pins −0.3 V to +3.6 V 202 Output Short-Circuit Duration Indefinite 10271- (Any Pin to Ground) Figure 2. Product Information on Package (Top View) Temperature Range Powered −40°C to +105°C
Table 4. Package Branding Information
Storage −40°C to +105°C
Branding Key Field Description
XL350B Part identifier for ADXL350 yw Date code Stresses above those listed under Absolute Maximum Ratings VVVV Factory lot code may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any
ESD CAUTION
other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE Table 3. Package Characteristics Package Type θ θ Device Weight JA JC
16-Terminal LGA_CAV 150°C/W 85°C/W 20 mg Rev. 0 | Page 4 of 36 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Package Information ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Power Sequencing Power Savings Power Modes Auto Sleep Mode Standby Mode Serial Communications SPI Preventing Bus Traffic Errors I2C Interrupts DATA_READY SINGLE_TAP DOUBLE_TAP Activity Inactivity FREE_FALL Watermark Overrun FIFO Bypass Mode FIFO Mode Stream Mode Trigger Mode Retrieving Data from FIFO Self-Test Register Map Register Definitions Register 0x00—DEVID (Read Only) Register 0x1D—THRESH_TAP (Read/Write) Register 0x1E, Register 0x1F, Register 0x20—OFSX, OFSY, OFSZ (Read/Write) Register 0x21—DUR (Read/Write) Register 0x22—Latent (Read/Write) Register 0x23—Window (Read/Write) Register 0x24—THRESH_ACT (Read/Write) Register 0x25—THRESH_INACT (Read/Write) Register 0x26—TIME_INACT (Read/Write) Register 0x27—ACT_INACT_CTL (Read/Write) ACT AC/DC and INACT AC/DC Bits ACT_x Enable Bits and INACT_x Enable Bits Register 0x28—THRESH_FF (Read/Write) Register 0x29—TIME_FF (Read/Write) Register 0x2A—TAP_AXES (Read/Write) Suppress Bit TAP_x Enable Bits Register 0x2B—ACT_TAP_STATUS (Read Only) ACT_x Source and TAP_x Source Bits Asleep Bit Register 0x2C—BW_RATE (Read/Write) LOW_POWER Bit Rate Bits Register 0x2D—POWER_CTL (Read/Write) Link Bit AUTO_SLEEP Bit Measure Bit Sleep Bit Wakeup Bits Register 0x2E—INT_ENABLE (Read/Write) Register 0x2F—INT_MAP (Read/Write) Register 0x30—INT_SOURCE (Read Only) Register 0x31—DATA_FORMAT (Read/Write) SELF_TEST Bit SPI Bit INT_INVERT Bit FULL_RES Bit Justify Bit Range Bits Register 0x32 to Register 0x37—DATAX0, DATAX1, DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only) Register 0x38—FIFO_CTL (Read/Write) FIFO_MODE Bits Trigger Bit Samples Bits 0x39—FIFO_STATUS (Read Only) FIFO_TRIG Bit Entries Bits Applications Information Power Supply Decoupling Mechanical Considerations for Mounting Tap Detection Threshold Link Mode Sleep Mode vs. Low Power Mode Offset Calibration Using Self-Test Axes of Acceleration Sensitivity Layout and Design Recommendations Outline Dimensions Ordering Guide