Datasheet ADXL356, ADXL357 (Analog Devices) - 32

ADXL356/ADXL357 Data Sheet ADXL357 REGISTER MAP
Note that while configuring the ADXL357 in an application, all configuration registers must be programmed before enabling measurement mode in the POWER_CTL register. When the ADXL357 is in measurement mode, only the fol owing configurations can change: the HPF_CORNER bits in the filter register, the INT_MAP register, the ST1 and ST2 bits in the SELF_TEST register, and the reset register.
Table 15. ADXL357 R egister Map Hex. Addr. Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset R/W
0x00 DEVID_AD DEVID_AD 0xAD R 0x01 DEVID_MST DEVID_MST 0x1D R 0x02 PARTID PARTID 0xED R 0x03 REVID REVID 0x01 R 0x04 Status Reserved NVM_ Activity FIFO_OVR FIFO_FULL DATA_RDY 0x00 R BUSY 0x05 FIFO_ENTRIES Reserved FIFO_ENTRIES 0x00 R 0x06 TEMP2 Reserved Temperature, Bits[11:8] 0x00 R 0x07 TEMP1 Temperature, Bits[7:0] 0x00 R 0x08 XDATA3 XDATA, Bits[19:12] 0x00 R 0x09 XDATA2 XDATA, Bits[11:4] 0x00 R 0x0A XDATA1 XDATA, Bits[3:0] Reserved 0x00 R 0x0B YDATA3 YDATA, Bits[19:12] 0x00 R 0x0C YDATA2 YDATA, Bits[11:4] 0x00 R 0x0D YDATA1 YDATA, Bits[3:0] Reserved 0x00 R 0x0E ZDATA3 ZDATA, Bits[19:12] 0x00 R 0x0F ZDATA2 ZDATA, Bits[11:4] 0x00 R 0x10 ZDATA1 ZDATA, Bits[3:0] Reserved 0x00 R 0x11 FIFO_DATA FIFO_DATA 0x00 R 0x1E OFFSET_X_H OFFSET_X, Bits[15:8] 0x00 R/W 0x1F OFFSET_X_L OFFSET_X, Bits[7:0] 0x00 R/W 0x20 OFFSET_Y_H OFFSET_Y, Bits[15:8] 0x00 R/W 0x21 OFFSET_Y_L OFFSET_Y, Bits[7:0] 0x00 R/W 0x22 OFFSET_Z_H OFFSET_Z, Bits[15:8] 0x00 R/W 0x23 OFFSET_Z_L OFFSET_Z, Bits[7:0] 0x00 R/W 0x24 ACT_EN Reserved ACT_Z ACT_Y ACT_X 0x00 R/W 0x25 ACT_THRESH_H ACT_THRESH, Bits[15:8] 0x00 R/W 0x26 ACT_THRESH_L ACT_THRESH, Bits[7:0] 0x00 R/W 0x27 ACT_COUNT ACT_COUNT 0x01 R/W 0x28 Filter Reserved HPF_CORNER ODR_LPF 0x00 R/W 0x29 FIFO_SAMPLES Reserved FIFO_SAMPLES 0x60 R/W 0x2A INT_MAP ACT_EN2 OVR_EN2 FULL_EN2 RDY_EN2 ACT_EN1 OVR_EN1 FULL_EN1 RDY_EN1 0x00 R/W 0x2B Sync Reserved EXT_CLK EXT_SYNC 0x00 R/W 0x2C Range I2C_HS INT_POL Reserved Range 0x81 R/W 0x2D POWER_CTL Reserved DRDY_OFF TEMP_OFF Standby 0x01 R/W 0x2E SELF_TEST Reserved ST2 ST1 0x00 R/W 0x2F Reset Reset 0x00 W Rev. 0 | Page 32 of 42 Document Outline Features Applications Functional Block Diagrams General Description Revision History Specifications Analog Output for the ADXL356 Digital Output for the ADXL357 SPI Digital Interface Characteristics for the ADXL357 I2C Digital Interface Characteristics for the ADXL357 Absolute Maximum Ratings Thermal Resistance Recommended Soldering Profile ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Root Allan Variance (RAV) ADXL357 Characteristics Theory of Operation Applications Information Analog Output Digital Output Axes of Acceleration Sensitivity Power Sequencing Power Supply Description VSUPPLY V1P8ANA V1P8DIG VDDIO Overrange Protection Self Test Filter Serial Communications SPI Protocol I2C Protocol Reading Acceleration or Temperature Data from the Interface FIFO Interrupts DATA_RDY DRDY Pin FIFO_FULL FIFO_OVR Activity NVM_BUSY External Synchronization and Interpolation EXT_SYNC = 00—No External Sync or Interpolation EXT_SYNC = 10—External Sync with Interpolation EXT_SYNC = 01—External Sync and External Clock, No Interpolation Filter ADXL357 Register Map Register Definitions Analog Devices ID Register Address: 0x00, Reset: 0xAD, Name: DEVID_AD Analog Devices MEMS ID Register Address: 0x01, Reset: 0x1D, Name: DEVID_MST Device ID Register Address: 0x02, Reset: 0xED, Name: PARTID Product Revision ID Register Address: 0x03, Reset: 0x01, Name: REVID Status Register Address: 0x04, Reset: 0x00, Name: Status FIFO Entries Register Address: 0x05, Reset: 0x00, Name: FIFO_ENTRIES Temperature Data Registers Address: 0x06, Reset: 0x00, Name: TEMP2 Address: 0x07, Reset: 0x00, Name: TEMP1 X-Axis Data Registers Address: 0x08, Reset: 0x00, Name: XDATA3 Address: 0x09, Reset: 0x00, Name: XDATA2 Address: 0x0A, Reset: 0x00, Name: XDATA1 Y-Axis Data Registers Address: 0x0B, Reset: 0x00, Name: YDATA3 Address: 0x0C, Reset: 0x00, Name: YDATA2 Address: 0x0D, Reset: 0x00, Name: YDATA1 Z-Axis Data Registers Address: 0x0E, Reset: 0x00, Name: ZDATA3 Address: 0x0F, Reset: 0x00, Name: ZDATA2 Address: 0x10, Reset: 0x00, Name: ZDATA1 FIFO Access Register Address: 0x11, Reset: 0x00, Name: FIFO_DATA X-Axis Offset Trim Registers Address: 0x1E, Reset: 0x00, Name: OFFSET_X_H Address: 0x1F, Reset: 0x00, Name: OFFSET_X_L Y-Axis Offset Trim Registers Address: 0x20, Reset: 0x00, Name: OFFSET_Y_H Address: 0x21, Reset: 0x00, Name: OFFSET_Y_L Z-Axis Offset Trim Registers Address: 0x22, Reset: 0x00, Name: OFFSET_Z_H Address: 0x23, Reset: 0x00, Name: OFFSET_Z_L Activity Enable Register Address: 0x24, Reset: 0x00, Name: ACT_EN Activity Threshold Registers Address: 0x25, Reset: 0x00, Name: ACT_THRESH_H Address: 0x26, Reset: 0x00, Name: ACT_THRESH_L Activity Count Register Address: 0x27, Reset: 0x01, Name: ACT_COUNT Filter Settings Register Address: 0x28, Reset: 0x00, Name: Filter FIFO Samples Register Address: 0x29, Reset: 0x60, Name: FIFO_SAMPLES Interrupt Pin (INTx) Function Map Register Address: 0x2A, Reset: 0x00, Name: INT_MAP Data Synchronization Address: 0x2B, Reset: 0x00, Name: Sync I2C Speed, Interrupt Polarity, and Range Register Address: 0x2C, Reset: 0x81, Name: Range Power Control Register Address: 0x2D, Reset: 0x01, Name: POWER_CTL Self Test Register Address: 0x2E, Reset: 0x00, Name: SELF_TEST Reset Register Address: 0x2F, Reset: 0x00, Name: Reset PCB Footprint Pattern Outline Dimensions Ordering Guide