LTC5587 ELECTRICAL CHARACTERISTICSThe l denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at TA = 25°C (Note 2). VCC = VDD = OVDD = 3.3V, VREF = 1.8V, EN = 3.3V, fSMPL =fSMPL(MAX) and fSCK = fSCK(MAX) unless otherwise noted. Test circuit is shown in Figure 1.SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS CIN SCK, CONV Input Capacitance 2 pF VOH SDO Logic High Output ISOURCE = 200μA l VDD – 0.2 V VOL SDO Logic Low Output ISINK = 200μA l 0.2 V IOZ Hi-Z Output Leakage CONV = VDD l ±3 μA COZ Hi-Z Output Capacitance CONV = VDD 4 pF ISOURCE SDO Source Current SDO Connected to GND = 0V –10 mA ISINK SDO Sink Current SDO Connected to VDD 10 mA Detector Enable (EN) Low = Off, High = OnPARAMETERCONDITIONSMINTYPMAXUNITS EN Input High Voltage (On) l 2 V EN Input Low Voltage (Off) l 0.3 V Enable Pin Input Current EN = 3.3V 25 μA Turn ON Time; CW RF Input VOUT within 10% of Final Value; PIN = 0dBm 1 μs Turn OFF Time; CW RF Input VOUT < 0.18V; PIN = 0dBm 8 μs Power Supply OVDD Supply Voltage l 1 3.3 VDD V VDD Supply Voltage l 2.7 3.3 3.6 V VREF Reference Voltage l 1.4 VDD + 0.05 V VCC Supply Voltage Should Be Equal to VDD l 2.7 3.3 3.6 V Total Supply Current No RF Input Signal, ADC Operational at 500ksps l 3 4 mA No RF Input Signal, ADC Sleep-Mode l 1.4 2.5 mA Shutdown Current EN = 0.3V, CONV = 3.3V, ADC Sleep-Mode 0.2 10 μA Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 6: PSRR determined as the dB value of the change in converted may cause permanent damage to the device. Exposure to any Absolute output voltage over the change in VCC supply voltage at a given CW input Maximum Rating condition for extended periods may affect device power level. reliability and lifetime. The maximum RF input power rating is guaranteed Note 7: Guaranteed by design not subject to test. by design and engineering characterization, but not production tested. Note 8: Guaranteed by characterization. All input signals are specified with Note 2: The LTC5587 is guaranteed to be functional over the operating tR = tF = 2ns (10% to 90% of VDD) and timed from a voltage level of 1.6V. temperature range from –40°C to 85°C. Note 9: All timing specifications given are with a 10pF capacitance load. Note 3: The linearity error is calculated by the difference between the With a capacitance load greater than this value, a digital buffer or latch incremental slope of the output and the average output slope from –20dBm must be used. to 0dBm. The dynamic range is defined as the range over which the Note 10: The time required for the output to cross the VIH or VIL voltage. linearity error is within ±1dB. Note 11: When pins VOUT and VREF are taken below GND or above VDD, Note 4: An external capacitor at the CSQ pin should be used for input they will be clamped by internal diodes. This product can handle input frequencies below 250MHz. Without this capacitor, lower frequency currents greater than 100mA below GND or above VDD without latchup. operation results in excessive RF ripple in the output voltage. Note 12: The VDD supply voltage can be the same as VCC and the pins can Note 5: Logarithmic intercept is an extrapolated input power level from share a common bypass capacitor of 2.2μF. the best fitted log-linear straight line, where the converted output code is 0LSB. 5587f 5 Document Outline FEATURES DESCRIPTION APPLICATIONS BLOCK DIAGRAM ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS BLOCK DIAGRAM TIMING DIAGRAMS TEST CIRCUIT APPLICATIONS INFORMATION PACKAGE DESCRIPTION TYPICAL APPLICATION RELATED PARTS