Datasheet LTC5587 (Analog Devices) - 4
| Fabricante | Analog Devices |
| Descripción | 6 GHz RMS Power Detector with Digital Output |
| Páginas / Página | 20 / 4 — ELECTRICAL CHARACTERISTICS. The. denotes the specifications which apply … |
| Formato / tamaño de archivo | PDF / 325 Kb |
| Idioma del documento | Inglés |
ELECTRICAL CHARACTERISTICS. The. denotes the specifications which apply over the full operating
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LTC5587
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VCC = VDD = OVDD = 3.3V, VREF = 1.8V, EN = 3.3V, fSMPL = fSMPL(MAX) and fSCK = fSCK(MAX) unless otherwise noted. Test circuit is shown in Figure 1. PARAMETER CONDITIONS MIN TYP MAX UNITS
Output Variation vs Temperature Normalized to Output at 25°C; PIN = –30dBm to 6dBm ±1 dB Output Variation vs Temperature Normalized to Output at 25°C; PIN = –27dBm to –10dBm ±0.5 dB Deviation from CW Response; WiMax OFDMA Preamble ±0.1 dB PIN = –34dBm to –4dBm WiMax OFDM Burst ±0.5 dB
Detector Analog Output
Output DC Voltage at VOUT No Signal Applied to RF Input 180 mV Output Impedance Internal Series Resistor Allows for Off-Chip Filter Cap 300 Ω Output Current Sourcing/Sinking 5/5 mA Rise Time (1000pF on VOUT) 0.2V to 1.6V, 10% to 90%, fRF = 2140MHz 1 μsec Fall Time (1000pF on VOUT) 1.6V to 0.2V, 10% to 90%, fRF = 2140MHz 8 μsec Power Supply Rejection Ratio (Note 6) For CW RF Input Over Operating Input Power Range 49 dB Integrated Output Voltage Noise 1 to 6.5 kHz Integration BW, PIN = 0dBm CW 150 μVRMS Peak-to-Peak ADC Output Noise CFILT = 1000pF, PIN = 0dBm CW 11 LSB
ADC Resolution
ADC Resolution (No Missing Codes) l 12 Bits Differential Linearity Error EN = 0V, Voltage on VOUT = 0V to 1.8V, VREF = 1.8V l ±0.25 ±1 LSB Measurement Resolution 1LSB = VREF/(4096 • 32mV/dB), VREF = 1.8V 0.014 dB/Bit
ADC Digital Timing SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPL(MAX) Maximum Sampling Frequency (Notes 8, 9) l 500 kHz fSCK Shift Clock Frequency (Notes 8, 9) l 50 MHz tSCK Shift Clock Period l 20 ns tTHROUGHPUT Minimum Throughput Time, tACQ + tCONV l 2 μs tACQ Acquisition Time l 0.5 μs tCONV Conversion Time l 1.5 μs t1 Minimum Positive CONV Pulse Width (Note 8) l 1.5 μs t2 SCK↑ Setup Time After CONV↓ (Note 8) l 16 ns t3 SDO Enabled Time After CONV↓ (Notes 8, 9) l 16 ns t4 SDO Data Valid Access Time After SCK↓ (Notes 8, 9, 10) l 8 ns t5 SCK Low Time (Note 7) l 40% tSCK t6 SCK High Time (Note 7) l 40% tSCK t7 SDO Data Valid Hold Time After SCK↓ (Notes 8, 9, 10) l 4 ns t8 SDO Into Hi-Z State Time After CONV↑ (Notes 8, 9) 6 ns
ADC Digital Inputs and Outputs SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH SCK, CONV Logic High Input l 2 V VIL SCK, CONV Logic Low Input l 0.8 V IIH Logic High Input Current SCK, CONV = VDD l 2.5 μA IIL Logic Low Input Current SCK, CONV = 0V l –2.5 μA 5587f 4 Document Outline FEATURES DESCRIPTION APPLICATIONS BLOCK DIAGRAM ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS BLOCK DIAGRAM TIMING DIAGRAMS TEST CIRCUIT APPLICATIONS INFORMATION PACKAGE DESCRIPTION TYPICAL APPLICATION RELATED PARTS
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VCC = VDD = OVDD = 3.3V, VREF = 1.8V, EN = 3.3V, fSMPL = fSMPL(MAX) and fSCK = fSCK(MAX) unless otherwise noted. Test circuit is shown in Figure 1. PARAMETER CONDITIONS MIN TYP MAX UNITS
Output Variation vs Temperature Normalized to Output at 25°C; PIN = –30dBm to 6dBm ±1 dB Output Variation vs Temperature Normalized to Output at 25°C; PIN = –27dBm to –10dBm ±0.5 dB Deviation from CW Response; WiMax OFDMA Preamble ±0.1 dB PIN = –34dBm to –4dBm WiMax OFDM Burst ±0.5 dB
Detector Analog Output
Output DC Voltage at VOUT No Signal Applied to RF Input 180 mV Output Impedance Internal Series Resistor Allows for Off-Chip Filter Cap 300 Ω Output Current Sourcing/Sinking 5/5 mA Rise Time (1000pF on VOUT) 0.2V to 1.6V, 10% to 90%, fRF = 2140MHz 1 μsec Fall Time (1000pF on VOUT) 1.6V to 0.2V, 10% to 90%, fRF = 2140MHz 8 μsec Power Supply Rejection Ratio (Note 6) For CW RF Input Over Operating Input Power Range 49 dB Integrated Output Voltage Noise 1 to 6.5 kHz Integration BW, PIN = 0dBm CW 150 μVRMS Peak-to-Peak ADC Output Noise CFILT = 1000pF, PIN = 0dBm CW 11 LSB
ADC Resolution
ADC Resolution (No Missing Codes) l 12 Bits Differential Linearity Error EN = 0V, Voltage on VOUT = 0V to 1.8V, VREF = 1.8V l ±0.25 ±1 LSB Measurement Resolution 1LSB = VREF/(4096 • 32mV/dB), VREF = 1.8V 0.014 dB/Bit
ADC Digital Timing SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPL(MAX) Maximum Sampling Frequency (Notes 8, 9) l 500 kHz fSCK Shift Clock Frequency (Notes 8, 9) l 50 MHz tSCK Shift Clock Period l 20 ns tTHROUGHPUT Minimum Throughput Time, tACQ + tCONV l 2 μs tACQ Acquisition Time l 0.5 μs tCONV Conversion Time l 1.5 μs t1 Minimum Positive CONV Pulse Width (Note 8) l 1.5 μs t2 SCK↑ Setup Time After CONV↓ (Note 8) l 16 ns t3 SDO Enabled Time After CONV↓ (Notes 8, 9) l 16 ns t4 SDO Data Valid Access Time After SCK↓ (Notes 8, 9, 10) l 8 ns t5 SCK Low Time (Note 7) l 40% tSCK t6 SCK High Time (Note 7) l 40% tSCK t7 SDO Data Valid Hold Time After SCK↓ (Notes 8, 9, 10) l 4 ns t8 SDO Into Hi-Z State Time After CONV↑ (Notes 8, 9) 6 ns
ADC Digital Inputs and Outputs SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH SCK, CONV Logic High Input l 2 V VIL SCK, CONV Logic Low Input l 0.8 V IIH Logic High Input Current SCK, CONV = VDD l 2.5 μA IIL Logic Low Input Current SCK, CONV = 0V l –2.5 μA 5587f 4 Document Outline FEATURES DESCRIPTION APPLICATIONS BLOCK DIAGRAM ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS BLOCK DIAGRAM TIMING DIAGRAMS TEST CIRCUIT APPLICATIONS INFORMATION PACKAGE DESCRIPTION TYPICAL APPLICATION RELATED PARTS