Datasheet LTC4315 (Analog Devices) - 8

LTC4315
OPERATION
The Block Diagram shows the major functional blocks and data pins for 95μs after that transition. A stop bit or of the LTC4315. The LTC4315 is a high noise margin bus bus idle is required on both sides to reactivate the buffers buffer which provides capacitance buffering for I2C signals. and RTAs. The precharge circuit is not affected by VCC2. Capacitance buffering is achieved by using back to back When a SDA/SCL pin is driven below the V buffers on the clock and data channels, which isolate IL level, the buffers are turned on and the logic low level is propagated the SDAIN and SCLIN capacitances from the SDAOUT though the LTC4315 to the other side. A high occurs when and SCLOUT capacitances respectively. All SDA and SCL all devices on the input and output sides release high. pins are fully bidirectional. The high noise margin allows Once the bus voltages rise above the V the LTC4315 to operate with non-compliant I2C devices IL level, the buffers are turned off. The RTAs are turned on at a slightly higher that drive a high VOL, permits a number of LTC4315s to voltage. The RTAs accelerate the rising edges of the SDA/ be connected in series and improves the reliability of I2C SCL inputs and outputs up to voltages of 0.9 • V communications in large noisy systems. When enabled, CC and 0.9 • V rise time accelerator (RTA) pull-up currents (I CC2 respectively, provided that the busses on their RTA) turn on own are rising at a minimum rate of 0.4V/μs as determined during rising edges to reduce bus rise time. In a typical by internal slew rate detectors. ACC is a three-state input application, the input bus is pulled up to VCC and the that controls the RTA pull-up current strength I output bus is pulled up to V RTA. CC2, although these are not requirements. V The LTC4315 detects a bus stuck low (fault) condition CC is the primary power supply to the LTC4315. V when both clock and data busses are not simultaneously CC and VCC2 serve as the input and output side rise time accelerator supplies respectively. Grounding V high at least once in 45ms. When a stuck bus occurs, the CC2 selectively disables the output side RTAs. LTC4315 asserts the FAULT flag. If DISCEN is tied high, the LTC4315 also disconnects the input and output sides and When the LTC4315 first receives power on its VCC pin, it after waiting at least 40μs, generates up to sixteen 5.5kHz starts out in an under voltage lockout mode (UVLO) until clock pulses on the SCLOUT pin and a stop bit to attempt its VCC exceeds 2.7V. The buffers and RTAs are disabled to free the stuck bus. Should the stuck bus release high and the LTC4315 ignores the logic state of its clock and during this period, clock generation is terminated and the data pins. During this time the precharge circuit forces a FAULT flag is cleared. nominal voltage of 1V on the SDA and SCL pins through 200k resistors. If DISCEN is tied low, a stuck bus event only causes FAULT flag assertion. Disconnection of the input and output sides Once the LTC4315 exits UVLO and its ENABLE pin has and clock generation are not done. Once the stuck bus been asserted high, it monitors the clock and data pins recovers and FAULT flag has been cleared, connection is for a stop bit or a bus idle condition. When a combination re-established between the input and output after a stop of either condition is detected simultaneously on the input bit or bus idle condition is detected. Toggling the ENABLE and output sides, the LTC4315 activates the connections pin after a fault condition has occurred forces a connec- between SDAIN and SDAOUT, and SCLIN and SCLOUT tion between the input and output. When powering into respectively, asserts READY high and deactivates the a stuck low condition, the input and output sides remain precharge circuit. If ACC is low or open, RTAs are also disconnected. After the timeout period, a stuck low fault enabled at this time. VCC2 transitions from a high to a low condition is detected and the behavior is as described or vice versa across a 1.8V threshold cause the LTC4315 previously. to disable the buffers and RTAs and to ignore the clock 4315f 8 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS BLOCK DIAGRAM OPERATION APPLICATIONS INFORMATION PACKAGE DESCRIPTION TYPICAL APPLICATION RELATED PARTS